From: Jie Luo <quic_luoj@quicinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Conor Dooley <conor@kernel.org>
Cc: <agross@kernel.org>, <andersson@kernel.org>,
<konrad.dybcio@linaro.org>, <davem@davemloft.net>,
<edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<conor+dt@kernel.org>, <andrew@lunn.ch>, <hkallweit1@gmail.com>,
<linux@armlinux.org.uk>, <robert.marko@sartura.hr>,
<linux-arm-msm@vger.kernel.org>, <netdev@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<quic_srichara@quicinc.com>
Subject: Re: [PATCH v2 5/5] dt-bindings: net: ipq4019-mdio: Document ipq5332 platform
Date: Fri, 15 Dec 2023 19:42:04 +0800 [thread overview]
Message-ID: <7466b655-2b7e-44f2-a510-6e0cc1b95248@quicinc.com> (raw)
In-Reply-To: <5a8095e6-b6a6-4d11-b006-31519e8d8622@linaro.org>
On 12/15/2023 6:53 PM, Krzysztof Kozlowski wrote:
> On 15/12/2023 11:40, Jie Luo wrote:
>>
>>
>> On 12/15/2023 6:37 PM, Krzysztof Kozlowski wrote:
>>> On 15/12/2023 11:33, Jie Luo wrote:
>>>>>>>>>>>> + cmn-reference-clock:
>>>>>>>>>>>> + oneOf:
>>>>>>>>>>>> + - items:
>>>>>>>>>>>> + - enum:
>>>>>>>>>>>> + - 0 # CMN PLL reference internal 48MHZ
>>>>>>>>>>>> + - 1 # CMN PLL reference external 25MHZ
>>>>>>>>>>>> + - 2 # CMN PLL reference external 31250KHZ
>>>>>>>>>>>> + - 3 # CMN PLL reference external 40MHZ
>>>>>>>>>>>> + - 4 # CMN PLL reference external 48MHZ
>>>>>>>>>>>> + - 5 # CMN PLL reference external 50MHZ
>>>>>>>>>>>> + - 6 # CMN PLL reference internal 96MHZ
>>>>>>>>>>>
>>>>>>>>>>> Why is this not represented by an element of the clocks property?
>>>>>>>>>>
>>>>>>>>>> This property is for the reference clock source selection of CMN PLL,
>>>>>>>>>> CMN PLL generates the different clock rates for the different Ethernet
>>>>>>>>>> blocks, this CMN PLL configuration is not located in the GCC, so the
>>>>>>>>>> clock framework can't be used, which is the general hardware register
>>>>>>>>>> instead of RCG register for GCC.
>>>>>>>>>
>>>>>>>>> I don't see how the clock being provided by the "GCC" (whatever that is)
>>>>>>>>> or by some other clock controller or fixed clock makes a difference.
>>>>>>>>> Why can't the other clock provider be represented in the devicetree?
>>>>>>>>>
>>>>>>>>
>>>>>>>> cmn-reference-clock is for selecting the reference clock source for the
>>>>>>>> whole Ethernet block, which is just the standalone configure register.
>>>>>>>
>>>>>>> Sure, you are aware though that all clocks are just configure registers?
>>>>>>>
>>>>>>> Which clocks are these mentioned in the property? From where do they come?
>>>>>>>
>>>>>>> Anyway, property is in existing form is not correct - this is not a
>>>>>>> generic property.
>>>>>>>
>>>>>>
>>>>>> This property cmn-reference-clock is just the hardware register
>>>>>> configuration, since the different IPQ platform needs to select
>>>>>> the different reference clock source for the CMN PLL block that
>>>>>> provides the various clock outputs to the all kinds of Ethernet
>>>>>> devices, which is not from GCC provider.
>>>>>
>>>>> AGAIN: where do the clocks come from? Which device generates them?
>>>>
>>>> Oh, OK, the reference clock is from wifi that provides 48MHZ to
>>>> Ethernet block.
>>>
>>> Then WiFi should be providing you the clock and this device should be
>>> clock consumer, right?
>>
>> Yes, wifi provides 48MHz clock to CMM PLL block, there is no GCC
>> for this 48MHZ clock output, it is the hardware PIN connection.
>
> All clocks are some hardware pin connections.
>
> Best regards,
> Krzysztof
>
Yes, all reference clocks here are from hardware pin connection.
next prev parent reply other threads:[~2023-12-15 11:42 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-12 11:51 [PATCH v2 0/5] support " Luo Jie
2023-12-12 11:51 ` [PATCH v2 1/5] net: mdio: ipq4019: move eth_ldo_rdy before MDIO bus register Luo Jie
2023-12-12 12:50 ` Maxime Chevallier
2023-12-12 19:11 ` Russell King (Oracle)
2023-12-13 10:07 ` Maxime Chevallier
2023-12-12 11:51 ` [PATCH v2 2/5] net: mdio: ipq4019: enable the SoC uniphy clocks for ipq5332 platform Luo Jie
2023-12-12 12:46 ` Maxime Chevallier
2023-12-13 8:05 ` Jie Luo
2023-12-12 11:51 ` [PATCH v2 3/5] net: mdio: ipq4019: configure CMN PLL clock for ipq5332 Luo Jie
2023-12-12 12:54 ` Maxime Chevallier
2023-12-12 19:12 ` Russell King (Oracle)
2023-12-13 8:09 ` Jie Luo
2023-12-13 10:08 ` Maxime Chevallier
2023-12-12 11:51 ` [PATCH v2 4/5] net: mdio: ipq4019: support MDIO clock frequency divider Luo Jie
2023-12-12 11:51 ` [PATCH v2 5/5] dt-bindings: net: ipq4019-mdio: Document ipq5332 platform Luo Jie
2023-12-12 13:24 ` Rob Herring
2023-12-12 16:06 ` Conor Dooley
2023-12-13 8:26 ` Jie Luo
2023-12-14 17:12 ` Conor Dooley
2023-12-15 6:46 ` Jie Luo
2023-12-15 7:29 ` Krzysztof Kozlowski
2023-12-15 9:49 ` Jie Luo
2023-12-15 10:19 ` Krzysztof Kozlowski
2023-12-15 10:33 ` Jie Luo
2023-12-15 10:37 ` Krzysztof Kozlowski
2023-12-15 10:40 ` Jie Luo
2023-12-15 10:53 ` Krzysztof Kozlowski
2023-12-15 11:42 ` Jie Luo [this message]
2023-12-15 12:19 ` Krzysztof Kozlowski
2023-12-15 12:40 ` Jie Luo
2023-12-15 13:39 ` Andrew Lunn
2023-12-16 13:31 ` Jie Luo
2023-12-15 13:41 ` Conor Dooley
2023-12-16 13:16 ` Jie Luo
2023-12-16 14:16 ` Conor Dooley
2023-12-16 15:37 ` Jie Luo
2023-12-19 15:47 ` Conor Dooley
2023-12-20 10:07 ` Jie Luo
2023-12-20 7:28 ` Krzysztof Kozlowski
2023-12-20 10:11 ` Jie Luo
2023-12-15 10:42 ` Conor Dooley
2023-12-15 11:42 ` Jie Luo
2023-12-12 20:06 ` Rob Herring
2023-12-13 8:42 ` Jie Luo
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