Re: [PATCH v3 0/7] KVM: x86/mmu: nVMX: 5-level paging cleanup and enabling

[Paolo Bonzini <pbonzini@redhat.com>]

On 03/03/20 03:02, Sean Christopherson wrote:
> Clean up MMU code related to 5 level paging, expose 5-level EPT to L1, and
> additional clean up on top (mostly renames of functions/variables that
> caused me no end of confusion when trying to figure out what was broken
> at various times).
> 
> v3:
>   - Dropped fixes for existing 5-level bugs (merged for 5.6).
>   - Use get_guest_pgd() instead of get_guest_cr3_or_eptp(). [Paolo]
>   - Add patches to fix MMU role calculation to play nice with 5-level
>     paging without requiring additional CR4.LA_57 bit.
> 
> v2:
>   - Increase the nested EPT array sizes to accomodate 5-level paging in
>     the patch that adds support for 5-level nested EPT, not in the bug
>     fix for 5-level shadow paging.
> 
> Sean Christopherson (7):
>   KVM: x86/mmu: Don't drop level/direct from MMU role calculation
>   KVM: x86/mmu: Drop kvm_mmu_extended_role.cr4_la57 hack
>   KVM: nVMX: Allow L1 to use 5-level page walks for nested EPT
>   KVM: nVMX: Rename nested_ept_get_cr3() to nested_ept_get_eptp()
>   KVM: nVMX: Rename EPTP validity helper and associated variables
>   KVM: x86/mmu: Rename kvm_mmu->get_cr3() to ->get_guest_pgd()
>   KVM: nVMX: Drop unnecessary check on ept caps for execute-only
> 
>  arch/x86/include/asm/kvm_host.h |  3 +-
>  arch/x86/include/asm/vmx.h      | 12 +++++++
>  arch/x86/kvm/mmu/mmu.c          | 59 +++++++++++++++++----------------
>  arch/x86/kvm/mmu/paging_tmpl.h  |  4 +--
>  arch/x86/kvm/svm.c              |  2 +-
>  arch/x86/kvm/vmx/nested.c       | 52 ++++++++++++++++++-----------
>  arch/x86/kvm/vmx/nested.h       |  4 +--
>  arch/x86/kvm/vmx/vmx.c          |  3 +-
>  arch/x86/kvm/x86.c              |  2 +-
>  9 files changed, 82 insertions(+), 59 deletions(-)
> 

Queued, thanks.  I have a cleanup on top to unify set_cr3 and
set_tdp_cr3, which I'll post after testing it.

Paolo