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Thu, 11 Aug 2022 01:05:00 -0700 (PDT) Received: from [192.168.1.39] ([83.146.140.105]) by smtp.gmail.com with ESMTPSA id y8-20020a2e95c8000000b0025d47a29734sm721935ljh.47.2022.08.11.01.04.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Aug 2022 01:05:00 -0700 (PDT) Message-ID: <74afb676-4a85-7a8e-f7ea-20d8a0967d7d@linaro.org> Date: Thu, 11 Aug 2022 11:04:59 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [PATCH 1/3] dt-bindings: display/msm: Add binding for SC8280XP MDSS Content-Language: en-US From: Krzysztof Kozlowski To: Bjorn Andersson , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Rob Herring , Krzysztof Kozlowski Cc: Sean Paul , David Airlie , Daniel Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220811040121.3775613-1-bjorn.andersson@linaro.org> <20220811040121.3775613-2-bjorn.andersson@linaro.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/08/2022 10:56, Krzysztof Kozlowski wrote: > On 11/08/2022 07:01, Bjorn Andersson wrote: >> Add binding for the display subsystem and display processing unit in the >> Qualcomm SC8280XP platform. >> >> Signed-off-by: Bjorn Andersson >> --- >> .../bindings/display/msm/dpu-sc8280xp.yaml | 284 ++++++++++++++++++ >> 1 file changed, 284 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml >> >> diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml >> new file mode 100644 >> index 000000000000..6c25943e639c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc8280xp.yaml > > qcom prefix is needed (also when file is in msm subdir) > > The file name should be based on compatible, so "qcom,sc8280xp-mdss.yaml" > >> @@ -0,0 +1,284 @@ >> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/display/msm/dpu-sc8280xp.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Qualcomm Display Processing Unit for SC8280XP >> + >> +maintainers: >> + - Bjorn Andersson >> + >> +description: >> + Device tree bindings for MSM Mobile Display Subsystem (MDSS) that encapsulates >> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree >> + bindings of MDSS and DPU are mentioned for SC8280XP. > > s/Device tree bindings// > so just: > > SC8280XP MSM Mobile Display Subsystem (MDSS) that encapsulates > sub-blocks like DPU display controller, DSI and DP interfaces etc. > >> + >> +properties: >> + compatible: >> + const: qcom,sc8280xp-mdss >> + >> + reg: >> + maxItems: 1 >> + >> + reg-names: >> + const: mdss > > You do not need reg names for one item, especially if the name is kind > of obvious... unless you re-use existing driver which needs it? Then > maybe let's change the driver to take first element? OK, I see the driver expects this. It seems it is legacy from 87729e2a7871 ("drm/msm: unify MDSS drivers") times. So it could be changed to grab first element always (older MDSS with three reg items still has mdss_phys at first item). > >> + >> + power-domains: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: Display AHB clock from gcc >> + - description: Display AHB clock from dispcc >> + - description: Display core clock >> + >> + clock-names: >> + items: >> + - const: iface >> + - const: ahb >> + - const: core >> + >> + interrupts: >> + maxItems: 1 >> + >> + interrupt-controller: true >> + >> + "#address-cells": true >> + >> + "#size-cells": true > > I see other DPU bindings also specify both as "true". Why not a fixed > number (const)? > >> + >> + "#interrupt-cells": >> + const: 1 >> + >> + iommus: >> + items: >> + - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0 >> + >> + ranges: true >> + >> + interconnects: >> + minItems: 2 > > No need for minItems in such case. > >> + maxItems: 2 >> + >> + interconnect-names: >> + items: >> + - const: mdp0-mem >> + - const: mdp1-mem >> + >> + resets: >> + items: >> + - description: MDSS_CORE reset >> + >> +patternProperties: >> + "^display-controller@[0-9a-f]+$": >> + type: object >> + description: Node containing the properties of DPU. > > additionalProperties:false on this level > > which will point to missing properties (e.g. opp-table) I'll fix existing bindings which have similar issue. Best regards, Krzysztof