Re: [PATCH] ARM: dts: BCM5301X: Fix pin controller node

[Christian Lamparter <chunkeey@gmail.com>]

On 2020-08-19 06:23, Florian Fainelli wrote:
> The pin controller resources start at 0xc0 from the CRU base which is at
> 0x100 from th DMU base, for a final address of 0x1800_c1c0, whereas we
> are currently off by 0x100. The resource size of the CRU is also
> incorrect and should end at 0x248 bytes from 0x100 which is the start
> address. Finally, the compatibility strings defined for the
> pin-controller node should reflect the SoC being used.
> 
> Fixes: 9994241ac97c ("ARM: dts: BCM5301X: Describe Northstar pins mux controller")
> Reported-by: Christian Lamparter <chunkeey@gmail.com>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> Christian, can you test this as a preliminary patch for your Cisco
> Meraki MR32 series? Thanks!

Hm, it looks like this is more complicated than this. We should have 
looked at pinctrl-ns.c's ns_pinctrl_probe() [0] before calling it.

|	ns_pinctrl->regmap = syscon_node_to_regmap(of_get_parent(np));
|	if (IS_ERR(ns_pinctrl->regmap)) {
|		int err = PTR_ERR(ns_pinctrl->regmap);
|
|		dev_err(dev, "Failed to map pinctrl regs: %d\n", err);
|
|		return err;
|	}
|
|	if (of_property_read_u32(np, "offset", &ns_pinctrl->offset)) {
|		dev_err(dev, "Failed to get register offset\n");
|		return -ENOENT;
|	}

So, the ns_pinctrl_probe() takes the address of the parent node (cru)
and then looks for a "offset" property to add to this (which is missing
in the bcm5301x.dtsi [1]).

Thing is, for this to work, the parent-node should be a "simple-mfd" (so 
a regmap is created for the reg), right? This would also mean that the 
"reg" property in the pin-controller node is just cosmetic.

I guess the reason why this sort-of-works for me is because I'm using 
this MR32 with OpenWrt (Rafał Miłecki is probably using it too ;) ).

(Note: We should not forget to update the binding-documentation as well!)

BTW: I'll reply my findings for the i2c issue with the MR32 in the other 
mail.

> 
>   arch/arm/boot/dts/bcm4708.dtsi  | 4 ++++
>   arch/arm/boot/dts/bcm4709.dtsi  | 4 ++++
>   arch/arm/boot/dts/bcm5301x.dtsi | 8 ++++----
>   3 files changed, 12 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/bcm4708.dtsi b/arch/arm/boot/dts/bcm4708.dtsi
> index 1a19e97a987d..5064fe51e402 100644
> --- a/arch/arm/boot/dts/bcm4708.dtsi
> +++ b/arch/arm/boot/dts/bcm4708.dtsi
> @@ -43,6 +43,10 @@ cpu@1 {
>   
>   };
>   
> +&pinctrl {
> +	compatible = "brcm,bcm4708-pinmux";
> +};
> +
>   &uart0 {
>   	status = "okay";
>   };
> diff --git a/arch/arm/boot/dts/bcm4709.dtsi b/arch/arm/boot/dts/bcm4709.dtsi
> index e1bb8661955f..7417c275ea9d 100644
> --- a/arch/arm/boot/dts/bcm4709.dtsi
> +++ b/arch/arm/boot/dts/bcm4709.dtsi
> @@ -5,6 +5,10 @@
>   
>   #include "bcm4708.dtsi"
>   
> +&pinctrl {
> +	compatible = "brcm,bcm4709-pinmux";
> +};
> +
>   &uart0 {
>   	clock-frequency = <125000000>;
>   	status = "okay";
> diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi
> index 2d9b4dd05830..bf49943f504a 100644
> --- a/arch/arm/boot/dts/bcm5301x.dtsi
> +++ b/arch/arm/boot/dts/bcm5301x.dtsi
> @@ -402,14 +402,14 @@ dmu@1800c000 {
>   
>   		cru@100 {
>   			compatible = "simple-bus";
> -			reg = <0x100 0x1a4>;
> +			reg = <0x100 0x248>;
>   			ranges;
>   			#address-cells = <1>;
>   			#size-cells = <1>;
>   
> -			pin-controller@1c0 {
> -				compatible = "brcm,bcm4708-pinmux";
> -				reg = <0x1c0 0x24>;
> +			pinctrl: pin-controller@c0 {
> +				compatible = "brcm,bcm53012-pinmux";
> +				reg = <0xc0 0x24>;
>   				reg-names = "cru_gpio_control";
>   
>   				spi-pins {
> 

[0] 
<https://elixir.bootlin.com/linux/v5.9-rc1/source/drivers/pinctrl/bcm/pinctrl-ns.c#L302>

[1] 
<https://elixir.bootlin.com/linux/v5.9-rc1/source/arch/arm/boot/dts/bcm5301x.dtsi#L410>