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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f74c3b680sm2417829b3a.41.2026.04.16.00.20.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Apr 2026 00:20:35 -0700 (PDT) Message-ID: <750c7a05-76a3-4992-a539-fb3c41b56ec7@oss.qualcomm.com> Date: Thu, 16 Apr 2026 15:20:31 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 04/12] coresight: etm4x: exclude ss_status from drvdata->config To: Yeoreum Yun Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com References: <20260415165528.3369607-1-yeoreum.yun@arm.com> <20260415165528.3369607-5-yeoreum.yun@arm.com> <778a826b-918d-4f7c-95a9-1cdb013618d8@oss.qualcomm.com> Content-Language: en-US From: Jie Gan In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE2MDA2OCBTYWx0ZWRfX8zc++WEjI+xx w1/dSsaKzforkpvhSMJnaZV92A73BKoYoVGmPACNKmHx7tE6TKSFvw6EnpZvd+YNhpUMFKbC6Bc dVovTLE0Umfuw7qzQAuiN2vLiwjWsMR1daDSCZJG2A9upx84mILqPM4v/5bFXv1QoWjqmK45WRK lD1vM44pBEaB/nEz8VTRUM/inb5RLWNwmuWsu+7LcddV/ABU+otCfsJKNqOueym187w0Fu2YXRy woYmP93vjntjvaOA/pTILzwSIuz/yoQTuvh13Kr1LZqiyDNhhRiSkLj8L+a2LCvgphuO/vanpTz gqE2w91fswx9xk2vSRQs634OhAKixYKyrJCV2SJtdM2snjp2/HoI0QuhNbn9+UpIGlqGOVSTV51 HsfKR/f9egRqavIiwpqFFZcWoPb0a1qS8kTFAsC1iz9QUSDumLP3Bx1a5kHYh1g6Jb83clCBn6r aSRYsoMdVHN9vTsWvkA== X-Proofpoint-ORIG-GUID: 8biTLeb47DvgDdBP39lPCQelHSkktQTp X-Authority-Analysis: v=2.4 cv=Ipgutr/g c=1 sm=1 tr=0 ts=69e08dc5 cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=7CQSdrXTAAAA:8 a=KKAkSRfTAAAA:8 a=eToclKRzwCUNLeFNS-YA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 a=a-qgeE7W1pNrGK8U0ZQC:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: 8biTLeb47DvgDdBP39lPCQelHSkktQTp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-16_02,2026-04-13_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 bulkscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604160068 On 4/16/2026 2:54 PM, Yeoreum Yun wrote: > Hi Jie, > Hi Yeoreum, >> >> >> On 4/16/2026 12:55 AM, Yeoreum Yun wrote: >>> The purpose of TRCSSCSRn register is to show status of >>> the corresponding Single-shot Comparator Control and input supports. >>> That means writable field's purpose for reset or restore from idle status >>> not for configuration. >>> >>> Therefore, exclude ss_status from drvdata->config, move it to etm4x_caps >>> and rename it to ss_smp. >>> >>> This includes remove TRCSSCRn from configurable item and >>> remove saving in etm4_disable_hw(). >>> >>> Signed-off-by: Yeoreum Yun >>> --- >>> .../hwtracing/coresight/coresight-etm4x-cfg.c | 1 - >>> .../coresight/coresight-etm4x-core.c | 19 ++++++------------- >>> .../coresight/coresight-etm4x-sysfs.c | 7 ++----- >>> drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++++++- >>> 4 files changed, 14 insertions(+), 20 deletions(-) >>> >>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c >>> index c302072b293a..d14d7c8a23e5 100644 >>> --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c >>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c >>> @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, >>> off_mask = (offset & GENMASK(11, 5)); >>> do { >>> CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask); >>> - CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask); >>> CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask); >>> } while (0); >>> } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) { >>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> index b2b092a76eb5..f55338a4989d 100644 >>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> @@ -91,7 +91,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) >>> const struct etmv4_caps *caps = &drvdata->caps; >>> return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp && >>> - (drvdata->config.ss_status[n] & TRCSSCSRn_PC); >>> + (caps->ss_cmp[n] & TRCSSCSRn_PC); >>> } >>> u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) >>> @@ -573,11 +573,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) >>> etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); >>> for (i = 0; i < caps->nr_ss_cmp; i++) { >>> - /* always clear status bit on restart if using single-shot */ >>> - if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) >>> - config->ss_status[i] &= ~TRCSSCSRn_STATUS; >>> etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); >>> - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); >>> + /* always clear status and pending bits on restart if using single-shot */ >>> + etm4x_relaxed_write32(csa, 0x0, TRCSSCSRn(i)); >>> if (etm4x_sspcicrn_present(drvdata, i)) >>> etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); >>> } >>> @@ -1055,12 +1053,6 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata) >>> etm4_disable_trace_unit(drvdata); >>> - /* read the status of the single shot comparators */ >>> - for (i = 0; i < caps->nr_ss_cmp; i++) { >>> - config->ss_status[i] = >>> - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); >>> - } >>> - >>> /* read back the current counter values */ >>> for (i = 0; i < caps->nr_cntr; i++) { >>> config->cntr_val[i] = >>> @@ -1503,8 +1495,9 @@ static void etm4_init_arch_data(void *info) >>> */ >>> caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); >>> for (i = 0; i < caps->nr_ss_cmp; i++) { >>> - drvdata->config.ss_status[i] = >>> - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); >>> + caps->ss_cmp[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i)); >>> + caps->ss_cmp[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV | >>> + TRCSSCSRn_DA | TRCSSCSRn_INST); >> >> Just re-go through this patch and had a question here: >> >> I’m not sure whether this new change should be documented in the ABI, given >> that the TRCSSCSRn_STATUS bit is masked. In my opinion, this change breaks >> the existing ABI description. >> >> Description from the ABI document: >> >> What: /sys/bus/coresight/devices/etm/sshot_status >> Date: December 2019 >> KernelVersion: 5.5 >> Contact: Mathieu Poirier >> Description: (Read) Print the current value of the selected single >> shot status register. > > But, as I mentioned another thread: > - https://lore.kernel.org/all/ad5yV2FoNbGGLE6R@e129823.arm.com/ > > Till now, sysfs doesn't show the *current value* of the single shot > state since the config->ss_status is updated enabled/disabled sysfs > session. an I think once the session is disabled, other status bits > (currently STATUS and PENDING bits) don't have any meaning. > > I think it's enough to change the doc's Description for this. > > Any thought? Thanks for the info. I have missed this info, we are calling it 'comparator' instead of 'status' by focusing on the capability bits. Make sense to me. Thanks, Jie > > -- > Sincerely, > Yeoreum Yun