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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: TrC1ucZ2r9VxbE1Q5rf5Y3RzRd8P8lIf X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzAyMDEwMiBTYWx0ZWRfXy0qN3hh8OZE9 u32CkjnMqjw9AB8x1NDb7M81gJeB8po9rt1v3y30zKW/sPZmdjQ8HWTVf1T7yDxEHvFSa06DcxL FpK6YTadL0mMqWVyrggkVv+xsQSxRQ/or80hiXemgyawQSC3qh7qPJ1MI0NA9+BOJF/GqfB1u4o h6cJT1zKz4758CzHOYfKgK7P5Zk97qDtS2n2O0JUyTBrhgnsgBspgTjOi69OCEaqwMT+dxbvlAV Ih1Czod3HWPTBf5naDdipcAL7UyKNeST6py4TeqgjdCfnRI/g7cCiPpkUUCtuWGXQninLEQMXDc /ffVvlGyHA0FAWpb3PD3lrd3tljWKQW+AihEWJQpV/YOnyt8YBGDqwVitCFzSt+Y4NGzoPK2NBd HBizwZmJiiJX4ti6YaLKYzaeR99hNs+KyqKVklbG8Cyx9BjXFR8Cx1SRRYZZ0fvGER7TVDzhv0+ SN7v4dGQJOAaOYAPZoA== X-Proofpoint-GUID: TrC1ucZ2r9VxbE1Q5rf5Y3RzRd8P8lIf X-Proofpoint-Spam-Info: AW1haW4tMjYwNzAyMDEwMiBTYWx0ZWRfXxGgw9WEDcGyD gpL2qQ+Jbhic/HW0fPqzaPORJBBj+DI5llyFsTrzvGu56ZpV0g499jArVvHAhDlRE21raWJkv9A 8Mvy/OYdjQX3mIDSKlJ7mHb4McBi79E= X-Authority-Analysis: v=2.4 cv=bdFbluPB c=1 sm=1 tr=0 ts=6a463571 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=1qKOYMtCOh3zOq8T1Y2cZw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=UCYWkEfTB1DHydHpn7IA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-07-02_01,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607020102 On 6/11/2026 2:34 PM, Konrad Dybcio wrote: > On 6/10/26 1:15 PM, Monish Chunara wrote: >> From: Monish Chunara >> >> Add support for SD card on Glymur SoC and enable the required pinctrl >> configurations. >> >> Co-developed-by: Sachin >> Signed-off-by: Sachin > > Firstname Lastname? The mentioned name was the preferred full name of the co-developer. > >> Signed-off-by: Monish Chunara >> --- >> arch/arm64/boot/dts/qcom/glymur.dtsi | 91 ++++++++++++++++++++++++++++ >> 1 file changed, 91 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi >> index 20b49af7298e..0989fe39e7ef 100644 >> --- a/arch/arm64/boot/dts/qcom/glymur.dtsi >> +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi >> @@ -3927,6 +3927,57 @@ lpass_ag_noc: interconnect@7e40000 { >> #interconnect-cells = <2>; >> }; >> >> + sdhc_2: mmc@8804000 { >> + compatible = "qcom,glymur-sdhci", "qcom,sdhci-msm-v5"; >> + >> + reg = <0x0 0x08804000 0x0 0x1000>; > > nit: Let's drop the \n above ACK, corrected in v2: https://lore.kernel.org/all/20260702094056.3755467-1-mchunara@oss.qualcomm.com/ >> + >> + interrupts = , >> + ; >> + interrupt-names = "hc_irq", >> + "pwr_irq"; >> + >> + clocks = <&gcc GCC_SDCC2_AHB_CLK>, >> + <&gcc GCC_SDCC2_APPS_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "iface", >> + "core", >> + "xo"; >> + >> + iommus = <&apps_smmu 0xd00 0>; > > '0x0' for the second value as it's a mask, please > ACK, corrected in v2. >> + qcom,dll-config = <0x0007442c>; >> + qcom,ddr-config = <0x80040868>; >> + >> + power-domains = <&rpmhpd RPMHPD_CX>; >> + operating-points-v2 = <&sdhc2_opp_table>; >> + >> + interconnects = <&aggre3_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; >> + interconnect-names = "sdhc-ddr", >> + "cpu-sdhc"; >> + >> + bus-width = <4>; >> + dma-coherent; >> + >> + status = "disabled"; >> + >> + sdhc2_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-100000000 { >> + opp-hz = /bits/ 64 <100000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; > > The SDC doc says this should be 50 MHz> + Frequencies below 100 MHz would be taken care off by the 100 MHz opp entry. >> + opp-202000000 { >> + opp-hz = /bits/ 64 <202000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; > > And that this should be opp_nom > > But the clock plan doc has info that corresponds with the content of > your patch, please check which one is correct and file a request for > fixing the wrong one > > Konrad This has been checked from the clocks plan PoV and referenced based on similar architecture targets. Updated the corners in the v2 series. Thanks and Regards, Monish