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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3339885ca07sm46793290eec.1.2026.09.08.23.20.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 08 Sep 2026 23:20:04 -0700 (PDT) Message-ID: <7527e6c7-82ad-48f1-8329-5b9222c347e4@oss.qualcomm.com> Date: Wed, 9 Sep 2026 11:50:01 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] mailbox: qcom-cpucp: read mbox hardware register using readq() To: Sivansh Gupta Cc: Jassi Brar , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260908155039.1203344-1-sivansh.gupta@oss.qualcomm.com> Content-Language: en-US From: Sibi Sankar In-Reply-To: <20260908155039.1203344-1-sivansh.gupta@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA5MDA2OSBTYWx0ZWRfX1KYxIgeINUXm Dr8KQEIHxpcpimy7fRRpvOfDMKOA/+Qs2pPBKKovNDrX7Uk7V1QILiohuEU3Z/fF+WnFUwCfOsv NTMRa1my3N0rEun65NVMnnFdI1cgjIofsSDySpGfg0eBEfYdJ58Iv/w4jM1fuMWf1eq2UPNrREV 08zv12fejDKqudkQWM581xITcFbZphxd+wNHhpxxCy0HcnH8oW3Od+edvni21KSFT6h8rvC7eTO 0Qr13Y4cyv3Ly0z6RPX3+H3q/xinfJrcue+tVnqTQK/Y85TwU+2PCDENWE+AVJi5FoasChe7DHm tERisjL/YPM+XT67VZEMyNJlQX3Oe2YPhAjfQrZP3XXu85yU/c1L3DUrSZOeI5Bq38FSdrEbZ/7 jguFEdlJfGCqFuY/jnFFzogjGXu0yh5l9mulTf4WPfO4i8bAjaRPIhlYTZuL0v5QzhOBrDIBpIL WC3YZjF0lpufYIpU84Q== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA5MDA2OSBTYWx0ZWRfX8bUrh3c1/C+3 lzyNtLhjbCDgJZjn3k692BzK4Zk8RiHegjrlblS2sUNKGpBb+GG8ogoTJ7MZ+vpXG8xq3ma0PbZ 12Tzye5HRh8l//sWcjGwN05N8LAjcbs= X-Proofpoint-GUID: 7gWSCsxPrs6qIplQCzjX8m_adCSI-2lZ X-Authority-Analysis: v=2.4 cv=JY2Ma0KV c=1 sm=1 tr=0 ts=6aa0fa96 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=wY5xiLK02p6FFHcKSBAA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: 7gWSCsxPrs6qIplQCzjX8m_adCSI-2lZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-08_03,2026-09-08_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 adultscore=0 priorityscore=1501 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609090069 On 9/8/2026 9:20 PM, Sivansh Gupta wrote: > Mailbox hardware registers are 64 bit but the interrupt handler > currently reads only 32 bits with readl(). Use readq() to read > the complete register value and pass it to the mailbox client. Can you please add more details to the commit message? It doesn't describe how switching to 64 bit would help mailbox or it's clients at the moment. -Sibi > > Fixes: 0e2a9a03106c ("mailbox: Add support for QTI CPUCP mailbox controller") > Signed-off-by: Sivansh Gupta > --- > drivers/mailbox/qcom-cpucp-mbox.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c > index 7ffc40acea9b..f56a05149281 100644 > --- a/drivers/mailbox/qcom-cpucp-mbox.c > +++ b/drivers/mailbox/qcom-cpucp-mbox.c > @@ -61,7 +61,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) > status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); > > for_each_set_bit(i, (unsigned long *)&status, cpucp->mbox.num_chans) { > - u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); > + u64 val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i)); > struct mbox_chan *chan = &cpucp->chans[i]; > unsigned long flags; >