From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6CB240800F for ; Tue, 21 Jul 2026 08:08:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621334; cv=none; b=PXs6bqn4Gr06DcMl8EBpeiYU/mzwcVW054ksJM18RbuMNroSoT02IB5gZJQ8YsIVSiJi3P5ZuhEBUGUZttbnIUX9OXOaZ2N9SWWpH1qNN5KoAz0tKmA+CFEkj5YihFTFWwDYGnHbpMlX2TX0PHBVZ/bMwu9C9HWOEtEQmIl40uk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784621334; c=relaxed/simple; bh=7epGUakHd9vgyZ6iMECsavVCm/6k6UDuSzEMqXdZamY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WRzNg/NjIzMzM8tl5QLJ8UQ4nLvLBVl4z2Uxde38nrFTbFbOp1LglIb1+/eDsM7qq105D1OgqW0LwNJSnmYQcqbk1wCWnfWViHYTgJukWmX+MXTbkYh+1xO0oaIxAkmR0bN5KkQ4sxonbc9SdIl4ZtntTeDRRyVZaV00Ao8MVw8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=G49VJHlQ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="G49VJHlQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 82DB91F00A3D; Tue, 21 Jul 2026 08:08:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784621333; bh=dGPbgxMuHa76rni/DbWF3QMjKVe0aeH48EDoCLLwvwU=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=G49VJHlQVml1KRzJfrYc6qptPjj20d5kPciMWVLxNi67PEz1jCzjh9oktbab03e6V +N5RGQXIKQqDb3QOpaxK2pF17bu5M65lTzGyXSzLPX5sjUajVGKRDkImYoQsvwNTpX 70bSWjBCE3HlTkUL9r/NCuV93v+F43uAOVp6P3d4ybPae7CpF1KzQtJzX8jbjdLPq4 lHhJ1HtIu+ks0Y1vRMRE8azbgrcIFVuHX80oXRUTANWJ+lVdDfCp/8yamCAH3qvyj4 hwhURFapvxgeVkBY6bKnxghcn3wtpQJL2bwvZKVOCU0szfwZY5t0ouZ+b4frK/c7/r 8NYgNqFgtFVjQ== From: "Naveen N Rao (AMD)" To: Borislav Petkov , Dave Hansen Cc: , , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , "H. Peter Anvin" , Thomas Gleixner Subject: [PATCH v3 3/3] x86/apic: Drop APIC_EILVT_NR_MAX and switch to using apic_eilvt_count Date: Tue, 21 Jul 2026 13:33:37 +0530 Message-ID: <754242d35fd6a5d3fe39e7de96ca4e813d100acc.1784619898.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Switch to using apic_eilvt_count as the maximum EILVT register count. Since this value is no longer a compile-time constant, update eilvt_offsets to be dynamically allocated. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/include/asm/apicdef.h | 1 - arch/x86/kernel/apic/apic.c | 7 +++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index ba7657e75ad1..32a242ae0455 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -140,7 +140,6 @@ #define APIC_IER 0x480 #define APIC_EILVTn(n) (0x500 + 0x10 * n) #define APIC_EILVT_NR_AMD_10H 4 -#define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) #define APIC_BASE_MSR 0x800 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 83895ce954ef..2e98ab259ae0 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -341,7 +341,7 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) * necessarily a BIOS bug. */ -static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +static atomic_t *eilvt_offsets; unsigned int apic_eilvt_count __ro_after_init; static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) @@ -355,7 +355,7 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new) { unsigned int rsvd, vector; - if (offset >= APIC_EILVT_NR_MAX) + if (!eilvt_offsets || offset >= apic_eilvt_count) return ~0; rsvd = atomic_read(&eilvt_offsets[offset]); @@ -418,6 +418,9 @@ static __init void init_eilvt(void) if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD) apic_eilvt_count = APIC_EILVT_NR_AMD_10H; + + if (apic_eilvt_count) + eilvt_offsets = kzalloc_objs(atomic_t, apic_eilvt_count); } /* -- 2.54.0