From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A41F33C52F for ; Wed, 4 Mar 2026 20:06:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772654787; cv=none; b=tCjN9lfqWvQGmdGTYQvBvFJTnSE4y068JuqHUOoS1/EHSdTO1vxLU96a3sQAFYioHeoRtC9ZBOo6ebszi85rQ+6pmFgSDrQYUYKWAK4B9I2bu9CtW+48eooIQ2lq8aO3HhFXKyjmH9VoBcEuDIpFh4BPTvhhfr95itF5QaUe3kU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772654787; c=relaxed/simple; bh=YjHQ0Iu/HvT6+/OF/ZjRkwFboR6C1zmMJpCB9HqJRQw=; h=Message-ID:Subject:From:To:Cc:Date:In-Reply-To:References: Content-Type:MIME-Version; b=hFuir3WQLD2q7sbQWHOM+FMnBypJFecxKQ9V2hIaPBstMv9j8y4e8fm62RuERvoyXmtP3g9pDnJfRZ2t0J4VwUbIyWM9kgNnPXk/OyyXI5WXfTWATwAnvF/eVB/36IPLH+pvCfk8uVOE7Ml9jgY9coBkbRvdRI3tVEj0+elJ4Ak= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NOC1Dbuq; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NOC1Dbuq" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1772654786; x=1804190786; h=message-id:subject:from:to:cc:date:in-reply-to: references:content-transfer-encoding:mime-version; bh=YjHQ0Iu/HvT6+/OF/ZjRkwFboR6C1zmMJpCB9HqJRQw=; b=NOC1DbuqTavGEjbZGH15Sy8uNs4Vs+QNkbtfX961JL3/IuhJXGUZx8Ix 7x9RN2IbII3TOQ6Nk8cH4hqGuGvjXS8h2bRO6BhXbobOmtKbtt1USRAul 8GXrIm1XHy5z5/IxLOo+4/vwdN7e7pcxr4+DiRrPFDt1GWLxZmC/n2ih6 zRGqdPC1jdPjnh4pgNE2lYx2LCwXAvateOPzU1pzozwXuMKIHQqP6LxJZ PuJqvsqMCo0MIEhcz82R4iOYsz3DwSiwHcc5wcbH35Rs/PGiIpMVhw25a dQ6yGoFnzI90Kljh8sbl87BrkvgGPjsAOO+dd7xdS44dDb4x/7xjTWfns g==; X-CSE-ConnectionGUID: ctfMN84wT+KkeB31A/ZiAw== X-CSE-MsgGUID: fA5MLzViSUa0gSgKlkAXkg== X-IronPort-AV: E=McAfee;i="6800,10657,11719"; a="85199085" X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="85199085" Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2026 12:06:26 -0800 X-CSE-ConnectionGUID: VUSTvsphSBy/o93IyD6Yfw== X-CSE-MsgGUID: KnN07GWQTbKsjLEmGuH2bw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,324,1763452800"; d="scan'208";a="217680838" Received: from abityuts-desk.ger.corp.intel.com (HELO [10.245.245.170]) ([10.245.245.170]) by orviesa010-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Mar 2026 12:06:22 -0800 Message-ID: <756d0e9d67750f2c7c46baba3763d692d8778f3a.camel@linux.intel.com> Subject: Re: [PATCH v3 1/4] mm/mmu_notifier: Allow two-pass struct mmu_interval_notifiers From: Thomas =?ISO-8859-1?Q?Hellstr=F6m?= To: "David Hildenbrand (Arm)" , intel-xe@lists.freedesktop.org Cc: Jason Gunthorpe , Andrew Morton , Simona Vetter , Dave Airlie , Alistair Popple , dri-devel@lists.freedesktop.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Matthew Brost , Christian =?ISO-8859-1?Q?K=F6nig?= Date: Wed, 04 Mar 2026 21:06:19 +0100 In-Reply-To: <07fb6811-68fe-4cb9-95e5-ded58a082493@kernel.org> References: <20260303133409.11609-1-thomas.hellstrom@linux.intel.com> <20260303133409.11609-2-thomas.hellstrom@linux.intel.com> <07fb6811-68fe-4cb9-95e5-ded58a082493@kernel.org> Organization: Intel Sweden AB, Registration Number: 556189-6027 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.58.3 (3.58.3-1.fc43) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2026-03-04 at 20:32 +0100, David Hildenbrand (Arm) wrote: > On 3/3/26 14:34, Thomas Hellstr=C3=B6m wrote: > > GPU use-cases for mmu_interval_notifiers with hmm often involve > > starting a gpu operation and then waiting for it to complete. > > These operations are typically context preemption or TLB flushing. > >=20 > > With single-pass notifiers per GPU this doesn't scale in > > multi-gpu scenarios. In those scenarios we'd want to first start > > preemption- or TLB flushing on all GPUs and as a second pass wait > > for them to complete. > >=20 > > One can do this on per-driver basis multiplexing per-driver > > notifiers but that would mean sharing the notifier "user" lock > > across all GPUs and that doesn't scale well either, so adding > > support > > for multi-pass in the core appears to be the right choice. > >=20 > > Implement two-pass capability in the mmu_interval_notifier. Use a > > linked list for the final passes to minimize the impact for > > use-cases that don't need the multi-pass functionality by avoiding > > a second interval tree walk, and to be able to easily pass data > > between the two passes. >=20 > Please CC all maintainers+reviewers that MAINTAINERS recommends you > to cc. Hmm. Good point. I missed a fair number of those. Will Resend Thanks, Thomas