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From: John Garry <john.g.garry@oracle.com>
To: Jing Zhang <renyu.zj@linux.alibaba.com>, Ian Rogers <irogers@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>,
	Will Deacon <will@kernel.org>, James Clark <james.clark@arm.com>,
	Mike Leach <mike.leach@linaro.org>, Leo Yan <leo.yan@linaro.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	Peter Zijlstra <peterz@infradead.org>,
	Ingo Molnar <mingo@redhat.com>,
	Arnaldo Carvalho de Melo <acme@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Alexander Shishkin <alexander.shishkin@linux.intel.com>,
	Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
	Andrew Kilroy <andrew.kilroy@arm.com>,
	Shuai Xue <xueshuai@linux.alibaba.com>,
	Zhuo Song <zhuo.song@linux.alibaba.com>
Subject: Re: [PATCH v6 1/7] perf vendor events arm64: Add common topdown L1 metrics
Date: Mon, 9 Jan 2023 14:58:35 +0000	[thread overview]
Message-ID: <758b66bb-6f9e-8a9a-8b0f-10cd79a65613@oracle.com> (raw)
In-Reply-To: <c2e5f9d7-c6d8-c70a-8eff-a8e1c5fcf0af@linux.alibaba.com>

On 09/01/2023 02:53, Jing Zhang wrote:
> I'll factor out the pmu_core__find function in tools/perf/arch/arm64/util/pmu.c:
> 
> static const struct perf_pmu *pmu_core__find(void)

maybe name as pmu_core__find_same() or similar to indicate that we're 
only dealing with homogeneous cores

> {
> 	struct perf_pmu *pmu = NULL;

no need to init to NULL

> 
> 	while ((pmu = perf_pmu__scan(pmu))) {

1x superfluous level of ()

> 		if (!is_pmu_core(pmu->name))
> 			continue;
> 
> 		/*
> 		 * The cpumap should cover all CPUs. Otherwise, some CPUs may
> 		 * not support some events or have different event IDs.
> 		 */
> 		if (pmu->cpus->nr != cpu__max_cpu().cpu)
> 			return NULL;
> 		return pmu;
> 	}
> 
> 	return NULL;
> }
> 

...

> 
>>> +}
>>> diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h
>>> index 69ca000..a2f7df8 100644
>>> --- a/tools/perf/util/pmu.h
>>> +++ b/tools/perf/util/pmu.h
>>> @@ -259,4 +259,5 @@ int perf_pmu__cpus_match(struct perf_pmu *pmu, struct perf_cpu_map *cpus,
>>>      char *pmu_find_real_name(const char *name);
>>>    char *pmu_find_alias_name(const char *name);
>>> +int perf_pmu__get_slots(void);
>> I think that this name is a bit too vague. Maybe perf_pmu__cpu_cycles_per_slot() could be better.
>>
> Does cpu_cycles_per_slot mean "cpu cycles per slot"? In the documemt, Slots mean operation width.
> If slots are 5, the largest value by which the STALL_SLOT PMU event may increment in one cycle is 5.
> So, maybe perf_pmu__cpu_slots_per_cycle() could be more accurate?

ok, yes, fine.

Thanks,
John


  reply	other threads:[~2023-01-09 14:59 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-06 15:05 [PATCH v6 0/7] Add metrics for neoverse-n2-v2 Jing Zhang
2023-01-06 15:05 ` [PATCH v6 1/7] perf vendor events arm64: Add common topdown L1 metrics Jing Zhang
2023-01-06 15:59   ` John Garry
2023-01-09  2:53     ` Jing Zhang
2023-01-09 14:58       ` John Garry [this message]
2023-01-10 10:38         ` Jing Zhang
2023-01-06 15:05 ` [PATCH v6 2/7] perf vendor events arm64: Add topdown L1 metrics for neoverse-n2-v2 Jing Zhang
2023-01-06 15:05 ` [PATCH v6 3/7] perf vendor events arm64: Add TLB " Jing Zhang
2023-01-06 15:05 ` [PATCH v6 4/7] perf vendor events arm64: Add cache " Jing Zhang
2023-01-06 15:05 ` [PATCH v6 5/7] perf vendor events arm64: Add branch " Jing Zhang
2023-01-06 15:05 ` [PATCH v6 6/7] perf vendor events arm64: Add PE utilization " Jing Zhang
2023-01-06 15:05 ` [PATCH v6 7/7] perf vendor events arm64: Add instruction mix " Jing Zhang

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