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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b353e5d155asm156475666b.6.2025.09.25.04.32.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Sep 2025 04:32:06 -0700 (PDT) Message-ID: <75d8cdc7-60c1-44a8-bf6c-0fb1ef38dd70@oss.qualcomm.com> Date: Thu, 25 Sep 2025 13:32:04 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 19/24] arm64: dts: qcom: glymur: Add support for PCIe5 To: Pankaj Patil , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prudhvi Yarlagadda , Qiang Yu References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> <20250925-v3_glymur_introduction-v1-19-24b601bbecc0@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250925-v3_glymur_introduction-v1-19-24b601bbecc0@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=B4a50PtM c=1 sm=1 tr=0 ts=68d52838 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=zO9y4h5Up0VuW54j_sAA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI1MDA0MiBTYWx0ZWRfX0N7jyrK62P8K IAquEynnU/m0/tBIBaHYTR+f0sIDPMOB+Yij9gZ2C/J2U/2ibS2tR1rFF0/2ig3YGxLgbq12SaR l8hJsSkvRDuUUDCV8U1uFHu1IomlPb/I+3UGfZMdzm31dHZjB1ng4uSFx12ayFxX2gmLKadR9j/ l8TCWR/LaRD6k3+5U+PsAhW+gFNpt/h3E6maKLXnhTRqgkoH4zEahzEU+QvmFkHvX1GVYGMyig+ nYMwR3TYH5UyncjPKifcNWc/19rda03peumjCwML9LdUZ7w29YBM8Z1Tgn8AG/q/ze41DhSVD9t NYHcUJILEA4TWtEBI3eJi8T0WVgH/8xkGxiFVbEgLdT6Zc5uYHwZHk9GaOdbIOFra0PXOLl6YZs R+inYecJ X-Proofpoint-GUID: pStQLm5uC-YS-SHneVub7uLn25-ptFdt X-Proofpoint-ORIG-GUID: pStQLm5uC-YS-SHneVub7uLn25-ptFdt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-25_01,2025-09-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 adultscore=0 phishscore=0 clxscore=1015 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509250042 On 9/25/25 8:32 AM, Pankaj Patil wrote: > From: Prudhvi Yarlagadda > > Describe PCIe5 controller and PHY. Also add required system resources like > regulators, clocks, interrupts and registers configuration for PCIe5. > > Signed-off-by: Prudhvi Yarlagadda > Signed-off-by: Qiang Yu > Signed-off-by: Pankaj Patil > --- [...] > + pcie5: pci@1b40000 { > + device_type = "pci"; > + compatible = "qcom,glymur-pcie", "qcom,pcie-x1e80100"; > + reg = <0x0 0x01b40000 0x0 0x3000>, > + <0x7 0xa0000000 0x0 0xf20>, > + <0x7 0xa0000f40 0x0 0xa8>, > + <0x7 0xb0000000 0x0 0x4000>, > + <0x7 0xa0100000 0x0 0x100000>, > + <0x0 0x01b43000 0x0 0x1000>; > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "config", > + "mhi"; > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x02000000 0 0x7a000000 0 0x7a000000 0 0x4000000>; No I/O space? We can also add the (presumably prefetchable) 64-bit range > + pcie5port0: pcie@0 { pcie5_port0: > + device_type = "pci"; > + reg = <0x0 0x0 0x0 0x0 0x0>; > + bus-range = <0x01 0xff>; > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges; > + phys = <&pcie5_phy>; same comment as on the other patch Konrad