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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-adec897acfasm345456766b.161.2025.06.14.12.19.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 14 Jun 2025 12:19:04 -0700 (PDT) Message-ID: <75fea0f5-88ca-4099-ba48-997e46bf4de5@oss.qualcomm.com> Date: Sat, 14 Jun 2025 21:19:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 07/10] clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Will Deacon , Catalin Marinas Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Dmitry Baryshkov References: <20250612-qcs615-mm-v9-clock-controllers-v9-0-b34dc78d6e1b@quicinc.com> <20250612-qcs615-mm-v9-clock-controllers-v9-7-b34dc78d6e1b@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250612-qcs615-mm-v9-clock-controllers-v9-7-b34dc78d6e1b@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: qKr1lxzZEmfXl-TTDO-1XlE2nAEelAiL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjE0MDE2MSBTYWx0ZWRfX01DZC8nM6gXw lt4Gd6T4AOSNyh3nKO3MHoDEuuw4MCK5ycteBmNm0tbVW/BY9YEZfO0VGCReAq+0XDZTJqueERm 0yRSLz3xazgXi9SehhKEnoeCT+BtXiDergfh/EUerL8dGJFI6yv/a5VK9n7oDI2iNIHW0ZIMos6 ruBVvlGN4IoDi2LTxg76yt+0GrKProFy9R3AbmMR5vC4kkUevJHv4S+1+f0cQGPglvlZFQhL7ha smkQAVj2gIA8tAl8ZEofVVtmRSzTlLcWyWAN2tEWMhGWIg1SmlpPKYwKv7Y6VI1I8gQd/H1z8iU uJlRzbcRYaxR1j5gxsmFE3IaQqEU365zIO/NkeLX/rv9LwNgmoIqEXDU2s8ea++RjdaU1s4+LeE e7RL9Z5xGDDgeAson+OkfINUD8PBGIzgrVrOAS14j4SCAsceUQp98eD0U7GFvrSzXyQGOfuW X-Authority-Analysis: v=2.4 cv=UL/dHDfy c=1 sm=1 tr=0 ts=684dcb2a cx=c_pps a=WeENfcodrlLV9YRTxbY/uA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=KKAkSRfTAAAA:8 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=3ze65spd1aMdTggYaI4A:9 a=QEXdDO2ut3YA:10 a=kacYvNCVWA4VmyqE58fU:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: qKr1lxzZEmfXl-TTDO-1XlE2nAEelAiL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-14_07,2025-06-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 phishscore=0 mlxlogscore=999 malwarescore=0 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506140161 On 6/12/25 11:55 AM, Taniya Das wrote: > Add support for the graphics clock controller for graphics clients to > be able to request for the clocks on QCS615 platform. > > Reviewed-by: Dmitry Baryshkov > Signed-off-by: Taniya Das > --- [...] > +struct clk_hw *gpu_cc_sm6150_hws[] = { "wink" [...] > +static void configure_crc(struct regmap *regmap) > +{ > + /* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */ > + regmap_update_bits(regmap, gpu_cc_cx_gmu_clk.clkr.enable_reg, 0xff0, 0xff0); > + > + /* > + * After POR, Clock Ramp Controller(CRC) will be in bypass mode. > + * Software needs to do the following operation to enable the CRC > + * for GFX3D clock and divide the input clock by div by 2. > + */ > + regmap_update_bits(regmap, 0x1028, 0x00015011, 0x00015011); > + regmap_update_bits(regmap, 0x1024, 0x00800000, 0x00800000); I'm going to assume this is not the same ramp controller as: drivers/soc/qcom/ramp_controller.c ..or maybe it is one, but we need to set things up on the CC side > +} > + > +static int gpu_cc_qcs615_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + > + regmap = qcom_cc_map(pdev, &gpu_cc_qcs615_desc); > + if (IS_ERR(regmap)) > + return PTR_ERR(regmap); > + > + clk_alpha_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); > + clk_alpha_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); > + > + /* Keep some clocks always enabled */ > + qcom_branch_set_clk_en(regmap, 0x1078); /* GPU_CC_AHB_CLK */ > + > + configure_crc(regmap); Likewise, please rebase on Jagadeesh's series, which is now in linux-next. With that: Reviewed-by: Konrad Dybcio Konrad