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From: Ninad Naik <quic_ninanaik@quicinc.com>
To: Bjorn Andersson <quic_bjorande@quicinc.com>,
	<konrad.dybcio@linaro.org>, <andersson@kernel.org>
Cc: <agross@kernel.org>, <linux-arm-msm@vger.kernel.org>,
	<linux-gpio@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<quic_ppareek@quicinc.com>, <psodagud@quicinc.com>,
	<quic_kprasan@quicinc.com>
Subject: Re: [PATCH] pinctrl: qcom: Add intr_target_width to define intr_target_bit field width
Date: Tue, 18 Jul 2023 10:38:53 +0530	[thread overview]
Message-ID: <760778dc-b0af-2adb-fa9e-4059a17a2cdf@quicinc.com> (raw)
In-Reply-To: <20230714203802.GA3972960@hu-bjorande-lv.qualcomm.com>

Hi,

Thank you all for the reviews.

On 7/15/2023 2:08 AM, Bjorn Andersson wrote:
> On Fri, Jul 14, 2023 at 11:40:09AM +0530, Ninad Naik wrote:
>> SA8775 and newer target have added support for an increased number of
>> interrupt targets. To implement this change, the intr_target field, which
>> is used to configure the interrupt target in the interrupt configuration
>> register is increased from 3 bits to 4 bits.
>>
>> In accordance to these updates, a new intr_target_width member is
>> introduced in msm_pingroup structure. This member stores the value of
>> width of intr_target field in the interrupt configuration register. This
>> value is used to dynamically calculate and generate mask for setting the
>> intr_target field. By default, this mask is set to 3 bit wide, to ensure
>> backward compatibility with the older targets.
>>
>> Signed-off-by: Ninad Naik <quic_ninanaik@quicinc.com>
> 
> Very nice, Ninad.
> 
> Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com>
> 
>> ---
>>   drivers/pinctrl/qcom/pinctrl-msm.c     | 9 ++++++---
>>   drivers/pinctrl/qcom/pinctrl-msm.h     | 2 ++
>>   drivers/pinctrl/qcom/pinctrl-sa8775p.c | 1 +
>>   3 files changed, 9 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
>> index 2585ef2b2793..6ebcaa2220af 100644
>> --- a/drivers/pinctrl/qcom/pinctrl-msm.c
>> +++ b/drivers/pinctrl/qcom/pinctrl-msm.c
>> @@ -1038,6 +1038,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
>>   	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
>>   	struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
>>   	const struct msm_pingroup *g;
>> +	u32 intr_target_mask = 0x7;
> 
> I like Konrad's suggestion about making this GENMASK(2, 0).
> 
> Please update that and include our R-b tags in v2.
> 
Sure, I'll change this to GENMASK and update all the relevant tags 
(Fixes and R-b) as suggested in the review comments.
> Regards,
> Bjorn

Thanks a lot!
Regards,
Ninad

      reply	other threads:[~2023-07-18  5:09 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-14  6:10 Ninad Naik
2023-07-14 14:32 ` Konrad Dybcio
2023-07-14 18:17 ` Andrew Halaney
2023-07-14 20:51   ` Bjorn Andersson
     [not found]   ` <BY5PR02MB6339C6B8A53C5D0CB55E58B7C034A@BY5PR02MB6339.namprd02.prod.outlook.com>
2023-07-14 21:04     ` FW: " Prasad Sodagudi
2023-07-14 22:39       ` Andrew Halaney
2023-07-14 20:38 ` Bjorn Andersson
2023-07-18  5:08   ` Ninad Naik [this message]

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