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Sun, 22 Feb 2026 22:18:19 -0800 From: Nicolin Chen To: CC: , , , , , , , , , , , Subject: [PATCH v12 3/8] iommu/arm-smmu-v3: Add an inline arm_smmu_domain_free() Date: Sun, 22 Feb 2026 22:18:04 -0800 Message-ID: <761dc017313fbd16b8bb446294e538af5313bb8f.1771815709.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001504:EE_|MN2PR12MB4471:EE_ X-MS-Office365-Filtering-Correlation-Id: 6b45e0dd-8ec8-4b5a-efba-08de72a36163 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|7416014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?+NmHkrMg1pOWncx+ozZLs5JZEH72+PBydkixyY1A/3lN4XvIaozKCJy0HwXW?= =?us-ascii?Q?X6DPqt1KmAuWQUXDTOhqSA3U5r+IUyG5D/64WMv6Bei8PwsiD79LYBupf2QC?= =?us-ascii?Q?Pl/2C589U0c7M4jWlLOMoUAcwwecEU0HvFlraGoJTTnyHYr9S/9qQvvhrC/8?= =?us-ascii?Q?dO68ImkVQJaUWGLvbMvvH0xK8kEqztoI4s+V27xuEajEXelsGdF1QnYNBkkj?= =?us-ascii?Q?j9jW575JOpcBXF7OGls+LpgQn6UyC69oZTfVa5wQxlzqW9XOwDZAD0Sjnoj2?= =?us-ascii?Q?EJiNP49OpHax5kLzKTgwFm5UW8Z7EZK2ySPSdZM0pGiqna3vbMF6UPOtFUyp?= =?us-ascii?Q?ifW7Xl/pjlbFkhh/TKtNjmhizuN+T1qlIMKVeY1HChjQ9KAxj/AfEqJvwz27?= =?us-ascii?Q?1QbtTjroLPeUZH4SLaJqDY9CV8KDybw5lt86rb/bP3dzjx/MO2f09dzx2BxU?= =?us-ascii?Q?01vt3zNxugSPtNrqmIUQ2CaUvP32DTM1RRa+3Tcj0pmRqXByycBLL6/pS0CP?= =?us-ascii?Q?AIGDG90L9nJmbNu3gsEf6tlg9YkKhOLJpIIcra7kKN/4MeVqBkl9qeTUaU1g?= =?us-ascii?Q?V56MC1cBc4zUbac3+O1mbu5cG2mmXpMPseyvb1rrLhOUSklcNN9N7ZwAOHEn?= =?us-ascii?Q?ccMABHmahjGK9xkWzpO/DDA6+DFue0HwgwVxV6Cp8gjlofPpurvW8lQbIGrd?= =?us-ascii?Q?Z1+2y05u8Q2kppCQwZNSFC+3/gn4i3Fm3FHlCih5yzVdu6/mv4CA3+SVn/8f?= =?us-ascii?Q?pywr51ZKHgg54AquuehMXwJpS21BE8Ob/6S7Yn9ZU3P6yGyPgjQXmyXsHyLJ?= =?us-ascii?Q?HcSCNQgdXHWRCOySyuRldtNCopljeQfjBkKrff6Un/VSbSdqy8QDA5P5l5di?= =?us-ascii?Q?ReZjxpdAxbuxYJ+cv8k85ccFv8e72kppXVnnA6vGkKQa3D9iH7yQamwfVV9s?= =?us-ascii?Q?a30+wtgqJj/7P7M0VQionMhsmiNPjLP4iitFeB8zP5PJLLt/RhhgB9IC2iZ3?= =?us-ascii?Q?sdX7R0gc3hw+aJuv0ME/WS1UxtU+kiCGbCyLt0bt8/i481lFrkNckhhI3HNH?= =?us-ascii?Q?qPYrI9xVyj3PPPMbpiQy7fr9FXquEpbm/iMMSaDAK7cPTgfubbwWfCWQEp4W?= =?us-ascii?Q?GNQvCAUzSJRiPWLPZNXl/6bxbWAokGFWZjyOV846x1ZhF14c7wCnQYV0dBGL?= =?us-ascii?Q?ZP61o1iI2E0U+6SstoP3GsKRapNlFy4jNrG/98XwyQ/fNYJzGL6yd1mJOMvG?= =?us-ascii?Q?5xsl5ETPJkXcdXCFm6Y8FGKPOlFNU98Rja634PkfJbmzVTbLbNZ4805jHRrZ?= =?us-ascii?Q?EwOfUr+dYZW/9c79EeMx2IQCWF33OwO5dmqh1L7JaG5paNl72WcjCQ3GeVBA?= =?us-ascii?Q?EnrP6Fuc8reyhVy0JtpGVRR7fiNv9xMWrIEPNu7iuNaY8hv0ddl0ayUkrIUB?= =?us-ascii?Q?1AZaEdpnGOiubUy/W4W3iUd7hJSrDduVlmbKF9skW2XKAaKGup8ofnY4GIeN?= =?us-ascii?Q?gLGPHdGtrHuYJf1GWFsLVvWXwFu0PaGBczki23AtzPBNT00xcV8q5F63kKB1?= =?us-ascii?Q?xs63CseeU5BCm1ram4syTFpfPDG9uWCFz1jewuy3EhgdKJZHpXU5GJ6HMjXW?= =?us-ascii?Q?tX7ocVVGTwLTGYqYhuhcacEMnZQ8511EOb7RP3r4U+cB96sez8uXrDePITtr?= =?us-ascii?Q?h2JknQ=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: GuaL0dZfamnPuD4HIso5hEsGMA2+yLUZOOpyvbEshIi75axSGktAS1wjKZIOiQF/0Qvcy0g1wqh3LZC7wP/OLRegTFzz8j6pKEhwZILJlNcrjb1wtEK8DpX1ubGUoYfimRFqI5MIfBILblr8mDEoCBnDibIvBJWDbBjdgmtM/jAutautZg71Vn0YWEB82uv2bqK59ChhlySboEywBNnvliM6T5f+DaD47MyX78XWtnkLsutQBy6ATpj3+nEIWZqH08ON5iqfLAyEMAUCk+ytEvp9JzjcfR8OmwwlTrcgVSl0B+vavsZrLnJIVYRvlMyEx6dnL0VJS40xbw8us1Os2Hv1Q79VzQzekkGSOQdKB3wzP4TDD152qgj20QyylWkuMgNDw9gkrB3F6lqL8xoPl11rwyA9eqmlJ2aiWVFzSC1BSuBPS6KjQm4Bc6A8lRTS X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Feb 2026 06:18:37.0804 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b45e0dd-8ec8-4b5a-efba-08de72a36163 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001504.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4471 There will be a bit more things to free than smmu_domain itself. So keep a simple inline function in the header to share aross files. Suggested-by: Jason Gunthorpe Reviewed-by: Jason Gunthorpe Acked-by: Balbir Singh Reviewed-by: Pranjal Shrivastava Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 5 +++++ drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 5 +++-- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 4 ++-- 3 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 24894b1630045..cfbedb76c8baa 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -956,6 +956,11 @@ extern struct mutex arm_smmu_asid_lock; struct arm_smmu_domain *arm_smmu_domain_alloc(void); +static inline void arm_smmu_domain_free(struct arm_smmu_domain *smmu_domain) +{ + kfree(smmu_domain); +} + void arm_smmu_clear_cd(struct arm_smmu_master *master, ioasid_t ssid); struct arm_smmu_cd *arm_smmu_get_cd_ptr(struct arm_smmu_master *master, u32 ssid); diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c index 6097f1f540d87..440ad8cc07de2 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c @@ -197,7 +197,8 @@ static void arm_smmu_mm_release(struct mmu_notifier *mn, struct mm_struct *mm) static void arm_smmu_mmu_notifier_free(struct mmu_notifier *mn) { - kfree(container_of(mn, struct arm_smmu_domain, mmu_notifier)); + arm_smmu_domain_free( + container_of(mn, struct arm_smmu_domain, mmu_notifier)); } static const struct mmu_notifier_ops arm_smmu_mmu_notifier_ops = { @@ -365,6 +366,6 @@ struct iommu_domain *arm_smmu_sva_domain_alloc(struct device *dev, err_asid: xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); err_free: - kfree(smmu_domain); + arm_smmu_domain_free(smmu_domain); return ERR_PTR(ret); } diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 117979c96b762..375f2143efc1d 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -2559,7 +2559,7 @@ static void arm_smmu_domain_free_paging(struct iommu_domain *domain) ida_free(&smmu->vmid_map, cfg->vmid); } - kfree(smmu_domain); + arm_smmu_domain_free(smmu_domain); } static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, @@ -3427,7 +3427,7 @@ arm_smmu_domain_alloc_paging_flags(struct device *dev, u32 flags, return &smmu_domain->domain; err_free: - kfree(smmu_domain); + arm_smmu_domain_free(smmu_domain); return ERR_PTR(ret); } -- 2.43.0