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Wed, 02 Jul 2025 17:46:56 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 562Hktgj030256 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 2 Jul 2025 17:46:55 GMT Received: from [10.50.58.161] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 2 Jul 2025 10:46:52 -0700 Message-ID: <7627d909-30d4-bf09-2736-a24bc91e28cf@quicinc.com> Date: Wed, 2 Jul 2025 23:16:49 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH] media: iris: Be explicit in naming of VPU2 power off handlers Content-Language: en-US To: Krzysztof Kozlowski , Dikshita Agarwal , Abhinav Kumar , "Bryan O'Donoghue" , Mauro Carvalho Chehab , , , References: <20250702134227.211104-2-krzysztof.kozlowski@linaro.org> <7ee61b56-4c93-f6e2-d405-9f88f69af675@quicinc.com> <85c3e526-b654-473c-82f7-0183e5fb5dd3@linaro.org> From: Vikash Garodia In-Reply-To: <85c3e526-b654-473c-82f7-0183e5fb5dd3@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: -0Hr8E2waxkaWrYWqZ-df6qaWo3-amgC X-Proofpoint-ORIG-GUID: -0Hr8E2waxkaWrYWqZ-df6qaWo3-amgC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzAyMDE0NyBTYWx0ZWRfXySl7Qut20PZX gNVQPjDrPZ5XnJf+I8nVsif5IdCYcIVaQY2dxLFQ6D8qFNvkTjI9eV5SFsov5ZU5r9R9N6umYNq t3cQYVl6HqPeSk77pdo8PfSu89CbSiD3A5OAzVFVVsE+w1G3WB1yqFkqqeCBm+Mp1ZeJ36WqHVA vyL2naovc30Xdp7iDfaZKL4/L0EV9z5C7Zl18bBZiRTtNCwGy6Mgrc3QZFncmx/k93SMpBWFf7y p7j3M2yTiglwZnVvmRKOxovn9awRF0TUzdwVoGJtcC9t1DkLIthPr2k7ME3lR8/UuA9mwQiculb qgqrEfMjyzamR6R08ceS5xvCdmIE6kSco7HjiBp9KO1ZM3+qwxeeKRLMnO42f3yNkn4VYMcZTut 9OqvE7vp30wwbWYdIrokbudlYJsFLh4b91eFBlDu+U2uGh7lY+uKpL3tmKa2Z7Rzg9e1U1TD X-Authority-Analysis: v=2.4 cv=QMFoRhLL c=1 sm=1 tr=0 ts=68657090 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=84x3ICFTYLOaS29QxbYA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.7,FMLib:17.12.80.40 definitions=2025-07-02_02,2025-07-02_04,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 bulkscore=0 spamscore=0 adultscore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 clxscore=1015 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507020147 On 7/2/2025 10:59 PM, Krzysztof Kozlowski wrote: > On 02/07/2025 19:20, Vikash Garodia wrote: >>> >>> const struct vpu_ops iris_vpu2_ops = { >>> - .power_off_hw = iris_vpu_power_off_hw, >>> - .power_off_controller = iris_vpu_power_off_controller, >>> + .power_off_hw = iris_vpu2_power_off_hw, >>> + .power_off_controller = iris_vpu2_power_off_controller, >> There was a reason to name it as VPU* independent, as it can be used for >> multiple VPUs. There isn't any VPU specific code within iris_vpu_power_off_hw >> that it needs to be associated to any VPU.>> >>> .calc_freq = iris_vpu2_calc_freq, >>> }; >>> diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c >>> index 9b7c9a1495ee..a2c8a1650153 100644 >>> --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c >>> +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c >>> @@ -104,7 +104,7 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) >>> writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); >>> >>> disable_power: >>> - iris_vpu_power_off_hw(core); >>> + iris_vpu2_power_off_hw(core); >> Again, its like VPU3 does something specific and then reuses the common handling. >> >> I do not see a point in making this change. > > The point is expressed in commit msg so address that. Also, this will > not be even correct for SM8750. When changes are raised for SM8750, the need of it can be reviewed then. Raise the patch for power off for SM8750 to review the incorrectness better. Regards, Vikash > >> >> Regards, >> Vikash >>> } >>> >>> static void iris_vpu33_power_off_hardware(struct iris_core *core) >>> @@ -142,7 +142,7 @@ static void iris_vpu33_power_off_hardware(struct iris_core *core) >>> writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); >>> > > Please kindly trim the replies from unnecessary context. It makes it > much easier to find new content. > > Best regards, > Krzysztof