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b=whsIL077aOxo/OY+4/XkP91Bjc26oVSD03fBZGFflnRiFH/UaNo55A/gR/8zErveyGLDmGlHXqz4tvyjY/tE+xZ/TIWZSvqNVyju9LbxJequlYweS+NNsiZonyTBMKg2j1Z0BPl1CsU54awja3vt21jmihbMZfgETbPJ+U1l7CI= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from MN0PR12MB6101.namprd12.prod.outlook.com (2603:10b6:208:3cb::10) by CH2PR12MB4954.namprd12.prod.outlook.com (2603:10b6:610:63::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5813.17; Mon, 14 Nov 2022 22:29:22 +0000 Received: from MN0PR12MB6101.namprd12.prod.outlook.com ([fe80::44a:a337:ac31:d657]) by MN0PR12MB6101.namprd12.prod.outlook.com ([fe80::44a:a337:ac31:d657%4]) with mapi id 15.20.5813.017; Mon, 14 Nov 2022 22:29:22 +0000 Message-ID: <76570217-12b0-0501-53b6-45100c3effe1@amd.com> Date: Mon, 14 Nov 2022 16:29:19 -0600 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.4.1 Subject: Re: [PATCH v4 9/9] Documentation: amd-pstate: add amd pstate driver mode introduction Content-Language: en-US To: Perry Yuan , rafael.j.wysocki@intel.com, ray.huang@amd.com, viresh.kumar@linaro.org Cc: Deepak.Sharma@amd.com, Nathan.Fontenot@amd.com, Alexander.Deucher@amd.com, Shimmer.Huang@amd.com, Xiaojian.Du@amd.com, Li.Meng@amd.com, wyes.karny@amd.com, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221110175847.3098728-1-Perry.Yuan@amd.com> <20221110175847.3098728-10-Perry.Yuan@amd.com> From: "Limonciello, Mario" In-Reply-To: <20221110175847.3098728-10-Perry.Yuan@amd.com> Content-Type: text/plain; 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On 11/10/2022 11:58, Perry Yuan wrote: > Introduce ``amd-pstate`` CPPC has two operation modes: > * CPPC Autonomous (active) mode > * CPPC non-autonomous (passive) mode. > active mode and passive mode can be choosed by whith different kernel parameters. can be chosen by different kernel parameters > > Signed-off-by: Perry Yuan > --- > Documentation/admin-guide/pm/amd-pstate.rst | 47 +++++++++++++++++++-- > 1 file changed, 43 insertions(+), 4 deletions(-) > > diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst > index e7488891b12f..6ba02a658b31 100644 > --- a/Documentation/admin-guide/pm/amd-pstate.rst > +++ b/Documentation/admin-guide/pm/amd-pstate.rst > @@ -302,11 +302,11 @@ efficiency frequency management method on AMD processors. > Kernel Module Options for ``amd-pstate`` > ========================================= > > -.. _shared_mem: > +.. legacy_cppc: > > -``shared_mem`` > -Use a module param (shared_mem) to enable related processors manually with > -**amd_pstate.shared_mem=1**. > +``legacy_cppc`` > +Use a module param (legacy_cppc) to enable related processors manually with > +**amd_pstate=legacy_cppc**. > Due to the performance issue on the processors with `Shared Memory Support > `_, we disable it presently and will re-enable this by default > once we address performance issue with this solution. > @@ -321,6 +321,45 @@ If the CPU flags have ``cppc``, then this processor supports `Full MSR Support > `_. Otherwise, it supports `Shared Memory Support `_. > > > +AMD Pstae Driver Operation Modes Pstate > +================================= > + > +``amd-pstate`` CPPC has two operation modes: CPPC Autonomous(active) mode and > +CPPC non-autonomous(passive) mode. > +active mode and passive mode can be choosed by whith different kernel parameters. can be chosen by different kernel parameters > +When in Autonomous mode, CPPC ignores requests done in the Desired Performance > +Target register and takes into account only the values set to the Minimum requested > +performance, Maximum requested performance, and Energy Performance Preference > +registers. When Autonomous is disabled, it only considers the Desired Performance Target. > + > +Active Mode > +------------ > + > +``amd-pstate-epp`` > + > +This is the low-level firmware control mode which is implemented by ``amd-pstate-epp`` > +driver with ``amd-pstate=active`` passed to the kernel in the command line. > +In this mode, ``amd-pstate-epp`` driver provides a hint to the hardware if software > +wants to bias toward performance (0x0) or energy efficiency (0xff) to the CPPC firmware. > +then CPPC power algorithm will calculate the runtime workload and adjust the realtime > +cores frequency according to the power supply and thermal, core voltage and some other > +hardware conditions. > + > +Passive Mode > +------------ > + > +``amd-pstate`` > + > +It will be enabled if the ``amd_pstate=passive`` is passed to the kernel in the command line. > +In this mode, ``amd-pstate``driver software specifies a desired QoS target in the CPPC > +performance scale as a relative number. This can be expressed as percentage of nominal > +performance (infrastructure max). Below the nominal sustained performance level, > +desired performance expresses the average performance level of the processor subject > +to the Performance Reduction Tolerance register. Above the nominal performance level, > +processor must provide at least nominal performance requested and go higher if current > +operating conditions allow. > + > + > ``cpupower`` tool support for ``amd-pstate`` > =============================================== >