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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: qL-ds54oJGHuWWvPBoxTe6qmaoMml8f8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAyNyBTYWx0ZWRfX+SdRCdOhlphQ Sv+1uyLwhvFevxEEMkFspv5R7FGaPM6Bz/zD1f+ir4QJFhYSGQWpaUFAMq0sLVx3QYOuOKFXTQQ 2W81OX3hVQXXrq0ffHaNBTlKC4ZF/N919wYGMU6qYAsy+gFuCctPEz8JTPQ0d0pelN0c0y41IBB ZsiIl70K+DrTwKggZkPeCc9w7I82TSZOwfwE8P0RaLeQSVUyVhm2UuWpCBqGG4XyF4yIrroWlHq 79l6MLLY+TdFiB/zTyxFXZEtbmf5neXks6U7+HciAcOKVjz6ZIhQ0LI2PlAUhFlVk0d4KkfrzUK UwJNe3pEpwkCbRGWgyW/gI0njRsZc1yNossyqEPxaWhZTOckXydJqloAlssIl/nBiRXAYY/nYOZ jBViGpYd5Ep8udC16nVBBGGFkURztA== X-Proofpoint-GUID: qL-ds54oJGHuWWvPBoxTe6qmaoMml8f8 X-Authority-Analysis: v=2.4 cv=EYjFgfmC c=1 sm=1 tr=0 ts=68f79b17 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=PLUc99ambSscJNFV4OcA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-21_02,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 spamscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 phishscore=0 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180027 On 10/19/2025 2:40 PM, Krzysztof Kozlowski wrote: > On 17/10/2025 19:08, Akhil P Oommen wrote: >> A612 GPU has a new IP called RGMU (Reduced Graphics Management Unit) >> which replaces GMU. But it doesn't do clock or voltage scaling. So we >> need the gpu core clock in the GPU node along with the power domain to >> do clock and voltage scaling from the kernel. Update the bindings to >> describe this GPU. >> >> Signed-off-by: Akhil P Oommen >> --- >> .../devicetree/bindings/display/msm/gpu.yaml | 31 ++++++++++++++++++++-- >> 1 file changed, 29 insertions(+), 2 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml >> index 3696b083e353031a496a1f299d8f373270ca562d..efc529e82bc198e7c3c89a5eecb6f929960a8de9 100644 >> --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml >> +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml >> @@ -45,11 +45,11 @@ properties: >> - const: amd,imageon >> >> clocks: >> - minItems: 2 >> + minItems: 1 >> maxItems: 7 >> >> clock-names: >> - minItems: 2 >> + minItems: 1 >> maxItems: 7 >> >> reg: >> @@ -388,6 +388,33 @@ allOf: >> required: >> - clocks >> - clock-names >> + >> + - if: >> + properties: >> + compatible: >> + contains: >> + const: qcom,adreno-612.0 >> + then: >> + properties: >> + clocks: >> + minItems: 1 > > Drop, it's implied. > > >> + maxItems: 1 >> + >> + clock-names: >> + items: >> + - const: core >> + description: GPU Core clock >> + > > Missing constraint for 'reg'. I suppose we should add reg property with a list of (items:) reg descriptions. No need for 'min/minxItems constraints as it is not flexible. > >> + reg-names: >> + minItems: 1 > > Drop. MMIO range is not flexible. Ack. -Akhil > >> + items: >> + - const: kgsl_3d0_reg_memory >> + - const: cx_dbgc >> + > Best regards, > Krzysztof