From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from vps0.lunn.ch (vps0.lunn.ch [156.67.10.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 55AAA2D46DF; Thu, 24 Jul 2025 12:53:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=156.67.10.101 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753361640; cv=none; b=dKPkBJqs3ZMPit12VcLd8xOo5FRtpaT0Rhmt3hjBzvomCLpP0UTXzqRKakc47LU4HWGe491FTuKpBu6L0V0OXSNJvDsMDCCWeE3CmoG+iuF+gE5HaLXLbepDUAYoMJprbkbA21fu7F8Aj+C+AftjYr9OZzdKAkF+tpW8Yq8C9ns= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1753361640; c=relaxed/simple; bh=4nKgSBvNF6KNqFuR3NRAg8Z96QH5x2/xGsDT5KpIPKI=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=KPLDNUDS1UEMY7NZM5Cy/f+Ufoyzy0wXSoalOk7YYNgc2z2OqTgjKnJSr8iLZjYKJ/NGKGGsy6GJdQOVA8umbAc4enweBgTwxGuRHl7dArNFyEoWOEB5gHVug5Z1Cvk8aY0MsTtY5dm3H4DJ1kmkGHIVI62cSd2lVqnaUSOiuBY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch; spf=pass smtp.mailfrom=lunn.ch; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b=ZBpdSnxs; arc=none smtp.client-ip=156.67.10.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=lunn.ch Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=lunn.ch Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch header.b="ZBpdSnxs" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch; s=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject: Date:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding: Content-ID:Content-Description:Content-Disposition:In-Reply-To:References; bh=n3/g4/jBSS+544GxD3Uqs3+ihWOI9sn+j4nRaeUAg7Y=; b=ZBpdSnxsorutDmupx/4WVEj1SW 1bm4a1Sl3LhmC7jKATKv6Bj5YVbhDxxMPBxAXZG6W+WhjzDrpfbfTQgHmOFy8klPSGkde/Myqk3Pb SHKyusWfHkjVxeysakRsTlCMlY406YskhV+RB00hIFeaHeEgYDfq9m/MRcdqhX6PzFYo=; Received: from andrew by vps0.lunn.ch with local (Exim 4.94.2) (envelope-from ) id 1uevS7-002lEV-5u; Thu, 24 Jul 2025 14:53:39 +0200 Date: Thu, 24 Jul 2025 14:53:39 +0200 From: Andrew Lunn To: Tao Ren Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joel Stanley , Andrew Jeffery , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org, Tao Ren Subject: Re: [PATCH v3 10/13] ARM: dts: aspeed: Add Facebook Fuji-data64 (AST2600) Board Message-ID: <769d6817-ee97-4a23-b013-29bc875a00cb@lunn.ch> References: <20250723233013.142337-1-rentao.bupt@gmail.com> <20250723233013.142337-11-rentao.bupt@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Wed, Jul 23, 2025 at 06:03:49PM -0700, Tao Ren wrote: > On Thu, Jul 24, 2025 at 02:03:20AM +0200, Andrew Lunn wrote: > > > +&mac3 { > > > + status = "okay"; > > > + phy-mode = "rgmii"; > > > > Does the PCB have extra long clock lines to implement the 2ns delay? > > > > Andrew > > Hi Andrew, > > Thank you for catching it. I didn't notice the settings because the file > is copied from the exiting fuji.dts with minor changes. > > The delay is currently introduced on MAC side (by manually setting SCU > registers), but I guess I can update phy-mode to "rgmii-id" so the delay > can be handled by the PHY? That would be good, if it works. The problem with the current code is that those SCU registers are not set as part of the MAC driver, so it is hard to know what value they have. Andrew