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Tue, 28 May 2024 23:07:21 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 44SN7IEf009714 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 May 2024 23:07:18 GMT Received: from [10.71.108.229] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 28 May 2024 16:07:17 -0700 Message-ID: <76b94146-1328-499c-9d17-4f2e8108556e@quicinc.com> Date: Tue, 28 May 2024 16:07:17 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/6] drm/msm/dpu: adjust data width for widen bus case Content-Language: en-US To: Jun Nie , Rob Clark , "Abhinav Kumar" , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , "Daniel Vetter" , Vinod Koul CC: , , , References: <20240527-msm-drm-dsc-dsi-video-upstream-4-v5-0-f797ffba4682@linaro.org> <20240527-msm-drm-dsc-dsi-video-upstream-4-v5-2-f797ffba4682@linaro.org> From: Jessica Zhang In-Reply-To: <20240527-msm-drm-dsc-dsi-video-upstream-4-v5-2-f797ffba4682@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: vLv8xHiONxaDkiG-Lali-YCIBFkea5A5 X-Proofpoint-GUID: vLv8xHiONxaDkiG-Lali-YCIBFkea5A5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.12.28.16 definitions=2024-05-28_14,2024-05-28_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 phishscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2405170001 definitions=main-2405280171 On 5/27/2024 7:21 AM, Jun Nie wrote: > data is valid for only half the active window if widebus > is enabled > > Signed-off-by: Jun Nie Hi Jun, Reviewed-by: Jessica Zhang Thanks, Jessica Zhang > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index 225c1c7768ff..f97221423249 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -168,6 +168,15 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, > > data_width = p->width; > > + /* > + * If widebus is enabled, data is valid for only half the active window > + * since the data rate is doubled in this mode. But for the compression > + * mode in DP case, the p->width is already adjusted in > + * drm_mode_to_intf_timing_params() > + */ > + if (p->wide_bus_en && !dp_intf) > + data_width = p->width >> 1; > + > hsync_data_start_x = hsync_start_x; > hsync_data_end_x = hsync_start_x + data_width - 1; > > > -- > 2.34.1 >