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X-CSE-ConnectionGUID: oJv9ss7TTqCaOIiVGLNPfQ== X-CSE-MsgGUID: WiDlbllVTgqANkrNaixB6A== X-IronPort-AV: E=McAfee;i="6800,10657,11911"; a="90485952" X-IronPort-AV: E=Sophos;i="6.27,114,1787036400"; d="scan'208";a="90485952" Received: from fmviesa013.fm.intel.com ([10.60.135.153]) by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2026 00:06:14 -0700 X-CSE-ConnectionGUID: bNJQaRoSQtaGEKTvysCowQ== X-CSE-MsgGUID: 9dwpuAJhQgSfjSLJTMuWYw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,114,1787036400"; d="scan'208";a="3831815" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.241.239]) ([10.124.241.239]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Sep 2026 00:06:11 -0700 Message-ID: <76c44332-2a6d-479f-aaf6-fab08e4cb60b@linux.intel.com> Date: Mon, 21 Sep 2026 15:06:08 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v9 10/12] perf/x86: Expose number of Topdown metric events to KVM To: Zide Chen , Sean Christopherson , Paolo Bonzini , Peter Zijlstra Cc: kvm@vger.kernel.org, Jim Mattson , Andi Kleen , Stephane Eranian , linux-kernel@vger.kernel.org, Mingwei Zhang , Das Sandipan , Shukla Manali , Xudong Hao References: <20260918193937.569414-1-zide.chen@intel.com> <20260918193937.569414-11-zide.chen@intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20260918193937.569414-11-zide.chen@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Reviewed-by: Dapeng Mi On 9/19/2026 3:39 AM, Zide Chen wrote: > The number of Topdown metric events varies by CPU: ICL/TGL/RKL > support 4, while SPR/GNR/DMR and some hybrid CPUs support 8. > > Add num_topdown_events to struct x86_pmu_capability and populate it > in perf_get_x86_pmu_capability() so that KVM can determine how many > PERF_METRICS fields are valid on the host CPU and correctly identify > the reserved bits in IA32_PERF_METRICS. > > Signed-off-by: Zide Chen > Cc: Peter Zijlstra > --- > v9: new patch > --- > arch/x86/events/core.c | 1 + > arch/x86/include/asm/perf_event.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index 8b3ea0adb965..01c1c9447f30 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -3164,6 +3164,7 @@ void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) > cap->events_mask_len = x86_pmu.events_mask_len; > cap->pebs_ept = x86_pmu.pebs_ept; > cap->mediated = !!(pmu.capabilities & PERF_PMU_CAP_MEDIATED_VPMU); > + cap->num_topdown_events = x86_pmu.num_topdown_events; > } > EXPORT_SYMBOL_FOR_KVM(perf_get_x86_pmu_capability); > > diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h > index ceb6188e5217..3c02389b2ea6 100644 > --- a/arch/x86/include/asm/perf_event.h > +++ b/arch/x86/include/asm/perf_event.h > @@ -306,6 +306,7 @@ struct x86_pmu_capability { > int bit_width_fixed; > unsigned int events_mask; > int events_mask_len; > + int num_topdown_events; > unsigned int pebs_ept :1; > unsigned int mediated :1; > };