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Fri, 6 Nov 2026 02:45:24 -0600 Received: from [192.168.1.149] (10.180.168.240) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server id 15.2.2562.53 via Frontend Transport; Fri, 6 Nov 2026 02:45:21 -0600 Message-ID: <76c9e2d2-ef9b-433c-9b84-201f43d3b940@amd.com> Date: Fri, 6 Nov 2026 14:15:19 +0530 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 1/3] iommu/amd: Drop unused global exclusion range fields and init To: Sairaj Kodilkar , "Joerg Roedel (AMD)" , Adrian Huang , Joerg Roedel , Robin Murphy , Suravee Suthikulpanit , Vasant Hegde , "Will Deacon" , , CC: Adam Pelka References: <20261106041650.24076-1-sarunkod@amd.com> <20261106041650.24076-2-sarunkod@amd.com> Content-Language: en-US From: "Jindal, Akshay" In-Reply-To: <20261106041650.24076-2-sarunkod@amd.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001D6:EE_|MW6PR12MB9017:EE_ X-MS-Office365-Filtering-Correlation-Id: ba229a96-dd33-4243-aa22-08df3be24daf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|23010399003|1800799024|376014|82310400026|261021130227099003|261021123027099003|261022115727099003|261022105027099003|261021133027099003|261022075727099003|261021135927099003|11063799006|261021121427099003|921020|261022113327099003|261009223027099003|261026130827099003|261026121527099003|261026135527099003|261028144727099003|261026140227099003|4143699003|10067099003|18002099003|261102123227099003|56012099006|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: avs8uwMFCvyB41ln+rOtmJYp8HR3Rn/Zoarrx0pHZio5vWMbHr2FcibUqcsDEUufn8Gr4TQie3v2OEY72T6ZeBiQlBAdBuciDsSWvustQT9X8uLKMkHcw7IDMg4e6kB8mdaEN3pPR39CJwBkB+Oz5AObtNVPXXccLIZ8M8HS9PDi2XevGNNg2TwQEHSN0bpTRuUT8pckUmNU9b2UP/5IDH5GfqhQ9QKvK5vs+E0C9Wcl/Xy6V+izL0Xf3To2tEHh1Oz8TfldgQw+VQ2ZC/LAFdjjzfHjZNrTmP/P45dm0QcRoFeOvp6zjm3iv+IrPmnelcNSjkJWI/VOuWgvbyYi1M8eQ3gCxuzX0XPyIhRUyhGTNzjTEBhfNSSGgRQbZ2eMJhLTxnEegRjtUhwmv6PllPR6vB3qCXOvkTif1Mw/n1+M4hQxAz4jZs7fdqTo26w+ X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2026 08:45:26.0632 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ba229a96-dd33-4243-aa22-08df3be24daf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001D6.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB9017 On 06-11-2026 09:46, Sairaj Kodilkar wrote: > Caution: This message originated from an External Source. Use proper caution when opening attachments, clicking links, or responding. > > > From: Suravee Suthikulpanit > > Remove unused struct amd_iommu.exclusion_start/exclusion_length, the > MMIO_EXCL_* flag masks, and iommu_set_exclusion_range(). These struct > amd_iommu fields were never assigned, so early_enable_iommu() never > programmed the hardware exclusion registers through this path. > > Please note that the exclusion range registers have been repurposed > to SNP completion-wait store base / limit registers. So, rename > MMIO_EXCL_BASE/LIMIT via to MMIO_COMPL_STORE_BASE/LIMIT instead. Reviewed-by: Akshay Jindal > > Signed-off-by: Suravee Suthikulpanit > Signed-off-by: Sairaj Kodilkar > Tested-by: Adam Pelka > --- > drivers/iommu/amd/amd_iommu_types.h | 4 ++-- > drivers/iommu/amd/init.c | 6 +++--- > 2 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h > index 8241ef922519..678ceddd711c 100644 > --- a/drivers/iommu/amd/amd_iommu_types.h > +++ b/drivers/iommu/amd/amd_iommu_types.h > @@ -44,8 +44,8 @@ > #define MMIO_CMD_BUF_OFFSET 0x0008 > #define MMIO_EVT_BUF_OFFSET 0x0010 > #define MMIO_CONTROL_OFFSET 0x0018 > -#define MMIO_EXCL_BASE_OFFSET 0x0020 > -#define MMIO_EXCL_LIMIT_OFFSET 0x0028 > +#define MMIO_COMPL_STORE_BASE_OFFSET 0x0020 > +#define MMIO_COMPL_STORE_LIMIT_OFFSET 0x0028 nit: 1. since it is SW based re-purpose and used in function iommu_set_cwwb_range() suggesting renaming to MMIO_CWWB_BASE_OFFSET & MMIO_CWWB_LIMIT_OFFSET > #define MMIO_EXT_FEATURES 0x0030 > #define MMIO_PPR_LOG_OFFSET 0x0038 > #define MMIO_GA_LOG_BASE_OFFSET 0x00e0 > diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c > index 8a410d4aa370..13c96feed64f 100644 > --- a/drivers/iommu/amd/init.c > +++ b/drivers/iommu/amd/init.c > @@ -370,14 +370,14 @@ static void iommu_set_cwwb_range(struct amd_iommu *iommu) > * Re-purpose Exclusion base/limit registers for Completion wait > * write-back base/limit. > */ > - memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, > + memcpy_toio(iommu->mmio_base + MMIO_COMPL_STORE_BASE_OFFSET, > &entry, sizeof(entry)); > > /* Note: > * Default to 4 Kbytes, which can be specified by setting base > * address equal to the limit address. > */ > - memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, > + memcpy_toio(iommu->mmio_base + MMIO_COMPL_STORE_LIMIT_OFFSET, > &entry, sizeof(entry)); > } > > @@ -1022,7 +1022,7 @@ static int __init remap_or_alloc_cwwb_sem(struct amd_iommu *iommu) > * completion wait buffer (CWB) address. Read and re-use it. > */ > pr_info_once("Re-using CWB buffers from the previous kernel\n"); > - paddr = readq(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET) & PM_ADDR_MASK; > + paddr = readq(iommu->mmio_base + MMIO_COMPL_STORE_BASE_OFFSET) & PM_ADDR_MASK; > iommu->cmd_sem = iommu_memremap(paddr, PAGE_SIZE); > if (!iommu->cmd_sem) > return -ENOMEM; > -- > 2.34.1 > >