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Thu, 16 Jan 2025 00:22:37 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50G0Ma8W023665 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 16 Jan 2025 00:22:36 GMT Received: from [10.71.108.79] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 15 Jan 2025 16:22:35 -0800 Message-ID: <76facac9-5db8-4dac-8aeb-099b0e4bc389@quicinc.com> Date: Wed, 15 Jan 2025 16:22:34 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 03/35] drm/msm/dpu: stop passing mdss_ver to setup_timing_gen() To: Dmitry Baryshkov , Rob Clark , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio CC: , , , References: <20241214-dpu-drop-features-v1-0-988f0662cb7e@linaro.org> <20241214-dpu-drop-features-v1-3-988f0662cb7e@linaro.org> Content-Language: en-US From: Abhinav Kumar In-Reply-To: <20241214-dpu-drop-features-v1-3-988f0662cb7e@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 5z9Ym2VIgyLKWOQavaf9KJrmLQxh2oHC X-Proofpoint-GUID: 5z9Ym2VIgyLKWOQavaf9KJrmLQxh2oHC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-15_10,2025-01-15_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 mlxscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501160001 On 12/13/2024 2:14 PM, Dmitry Baryshkov wrote: > As a preparation to further MDSS-revision cleanups stop passing MDSS > revision to the setup_timing_gen() callback. Instead store a pointer to > it inside struct dpu_hw_intf and use it diretly. It's not that the MDSS > revision can chance between dpu_hw_intf_init() and > dpu_encoder_phys_vid_setup_timing_engine(). > Not seeing anything wrong with this patch OR the need to absolutely do this either. Will revisit after rest of the series to see where we are going with this as the intention is not clear. > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 3 +-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 7 ++++--- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 5 +++-- > 3 files changed, 8 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > index abd6600046cb3a91bf88ca240fd9b9c306b0ea2e..3e0f1288ad17e19f6d0b7c5dcba19d3e5977a461 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c > @@ -307,8 +307,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( > > spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); > phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, > - &timing_params, fmt, > - phys_enc->dpu_kms->catalog->mdss_ver); > + &timing_params, fmt); > phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); > > /* setup which pp blk will connect to this intf */ > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > index fb1d25baa518057e74fec3406faffd48969d492b..1d56c21ac79095ab515aeb485346e1eb5793c260 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c > @@ -98,8 +98,7 @@ > > static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, > const struct dpu_hw_intf_timing_params *p, > - const struct msm_format *fmt, > - const struct dpu_mdss_version *mdss_ver) > + const struct msm_format *fmt) > { > struct dpu_hw_blk_reg_map *c = &intf->hw; > u32 hsync_period, vsync_period; > @@ -180,7 +179,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *intf, > > /* TODO: handle DSC+DP case, we only handle DSC+DSI case so far */ > if (p->compression_en && !dp_intf && > - mdss_ver->core_major_ver >= 7) > + intf->mdss_ver->core_major_ver >= 7) > intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; > > hsync_data_start_x = hsync_start_x; > @@ -580,6 +579,8 @@ struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev, > c->idx = cfg->id; > c->cap = cfg; > > + c->mdss_ver = mdss_rev; > + > c->ops.setup_timing_gen = dpu_hw_intf_setup_timing_engine; > c->ops.setup_prg_fetch = dpu_hw_intf_setup_prg_fetch; > c->ops.get_status = dpu_hw_intf_get_status; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h > index 114be272ac0ae67fe0d4dfc0c117baa4106f77c9..f31067a9aaf1d6b96c77157135122e5e8bccb7c4 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h > @@ -81,8 +81,7 @@ struct dpu_hw_intf_cmd_mode_cfg { > struct dpu_hw_intf_ops { > void (*setup_timing_gen)(struct dpu_hw_intf *intf, > const struct dpu_hw_intf_timing_params *p, > - const struct msm_format *fmt, > - const struct dpu_mdss_version *mdss_ver); > + const struct msm_format *fmt); > > void (*setup_prg_fetch)(struct dpu_hw_intf *intf, > const struct dpu_hw_intf_prog_fetch *fetch); > @@ -126,6 +125,8 @@ struct dpu_hw_intf { > enum dpu_intf idx; > const struct dpu_intf_cfg *cap; > > + const struct dpu_mdss_version *mdss_ver; > + > /* ops */ > struct dpu_hw_intf_ops ops; > }; >