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Wed, 21 Feb 2024 10:00:45 +0000 (UTC) Message-ID: <770b23ec-7199-4202-888d-6a22b7f4af74@collabora.com> Date: Wed, 21 Feb 2024 11:00:44 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] arm64: dts: mediatek: mt7981: add pinctrl Content-Language: en-US To: =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , Matthias Brugger , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Chen-Yu Tsai , Hsin-Yi Wang , =?UTF-8?Q?N=C3=ADcolas_F_=2E_R_=2E_A_=2E_Prado?= , Heiko Stuebner , Jernej Skrabec , Chris Morgan , Linus Walleij , Sean Wang , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= References: <20240221073524.20947-1-zajec5@gmail.com> <20240221073524.20947-4-zajec5@gmail.com> From: AngeloGioacchino Del Regno In-Reply-To: <20240221073524.20947-4-zajec5@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Il 21/02/24 08:35, Rafał Miłecki ha scritto: > From: Rafał Miłecki > > MT7981 contains on-SoC PIN controller that is also a GPIO provider. > > Signed-off-by: Rafał Miłecki > --- > arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 37 +++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi > index 4feff3d1c5f4..fdd5c22cfc9c 100644 > --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi > @@ -86,6 +86,43 @@ pwm@10048000 { > #pwm-cells = <2>; > }; > > + pio: pinctrl@11d00000 { > + compatible = "mediatek,mt7981-pinctrl"; > + reg = <0 0x11d00000 0 0x1000>, > + <0 0x11c00000 0 0x1000>, > + <0 0x11c10000 0 0x1000>, > + <0 0x11d20000 0 0x1000>, > + <0 0x11e00000 0 0x1000>, > + <0 0x11e20000 0 0x1000>, > + <0 0x11f00000 0 0x1000>, > + <0 0x11f10000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb", > + "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint"; > + interrupt-controller; > + interrupts = ; > + interrupt-parent = <&gic>; > + gpio-ranges = <&pio 0 0 56>; > + gpio-controller; > + #gpio-cells = <2>; > + #interrupt-cells = <2>; > + > + mdio-pins { > + mux { That's board specific. MDIO and SPI0 pins can be used as GPIO instead of, respectively, ETH and SPI. Must go to your board devicetree, not here: please move both. Cheers, Angelo > + function = "eth"; > + groups = "smi_mdc_mdio"; > + }; > + }; > + > + spi0-pins { > + mux { > + function = "spi"; > + groups = "spi0", "spi0_wp_hold"; > + }; > + }; > + > + }; > + > clock-controller@15000000 { > compatible = "mediatek,mt7981-ethsys", "syscon"; > reg = <0 0x15000000 0 0x1000>;