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From: Xi Pardee <xi.pardee@linux.intel.com>
To: Russell Haley <yumpusamongus@gmail.com>,
	irenic.rajneesh@gmail.com, david.e.box@linux.intel.com,
	hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com,
	platform-driver-x86@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org
Subject: Re: [PATCH v3 4/6] platform/x86:intel/pmc: Show substate requirement for S0ix blockers
Date: Fri, 5 Sep 2025 11:43:44 -0700	[thread overview]
Message-ID: <7714a30a-6505-43c8-949a-43f48049c1c9@linux.intel.com> (raw)
In-Reply-To: <60e6b6da-ba46-4a75-b571-8b62f3186008@gmail.com>

Hi Russell,

Thanks for the review.

On 9/1/2025 4:52 PM, Russell Haley wrote:
> On 8/15/25 5:46 PM, Xi Pardee wrote:
>> Add support to read and show S0ix blocker substate requirements.
>> Starting from Panther Lake, substate requirement data is provided
>> based on S0ix blockers instead of all low power mode requirements.
>> For platforms that support this new feature, add support to display
>> substate requirements based on S0ix blockers.
>>
>> Change the "substate_requirements" attribute of Intel PMC Core
>> driver to show the substate requirements for each S0ix blocker
>> and the corresponding S0ix blocker value.
>>
>> Signed-off-by: Xi Pardee <xi.pardee@linux.intel.com>
>> ---
>>   drivers/platform/x86/intel/pmc/arl.c  |   4 +
>>   drivers/platform/x86/intel/pmc/core.c | 126 ++++++++++++++++++++++++--
>>   drivers/platform/x86/intel/pmc/core.h |  14 +++
>>   drivers/platform/x86/intel/pmc/lnl.c  |   2 +
>>   drivers/platform/x86/intel/pmc/mtl.c  |   2 +
>>   5 files changed, 138 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/platform/x86/intel/pmc/arl.c b/drivers/platform/x86/intel/pmc/arl.c
>> index 9d66d65e75779..17ad87b392abe 100644
>> --- a/drivers/platform/x86/intel/pmc/arl.c
>> +++ b/drivers/platform/x86/intel/pmc/arl.c
>> @@ -725,9 +725,11 @@ struct pmc_dev_info arl_pmc_dev = {
>>   	.dmu_guid = ARL_PMT_DMU_GUID,
>>   	.regmap_list = arl_pmc_info_list,
>>   	.map = &arl_socs_reg_map,
>> +	.sub_req_show = &pmc_core_substate_req_regs_fops,
>>   	.suspend = cnl_suspend,
>>   	.resume = arl_resume,
>>   	.init = arl_core_init,
>> +	.sub_req = pmc_core_pmt_get_lpm_req,
>>   };
>>   
>>   struct pmc_dev_info arl_h_pmc_dev = {
>> @@ -735,7 +737,9 @@ struct pmc_dev_info arl_h_pmc_dev = {
>>   	.dmu_guid = ARL_PMT_DMU_GUID,
>>   	.regmap_list = arl_pmc_info_list,
>>   	.map = &mtl_socm_reg_map,
>> +	.sub_req_show = &pmc_core_substate_req_regs_fops,
>>   	.suspend = cnl_suspend,
>>   	.resume = arl_h_resume,
>>   	.init = arl_h_core_init,
>> +	.sub_req = pmc_core_pmt_get_lpm_req,
>>   };
> The cover letter and commit messages say Panther Lake, but I see a bunch
> of "arl" here. Is this just confusing file and struct names, or is my
> Arrow Lake 265K getting idle-blocker-cause debug info? If so it should
> probably be mentioned in the changelog.
>
> Same question about patch 5.

This patch series enables SSRAM supports of Lunar Lake and Panther Lake 
platforms in intel_pmc_core driver. It would not modify the 
functionality of intel_pmc_core driver in Arrow Lake platforms. Arrow 
Lake would not get s0ix_blocker information with this patch series.

Starting from Panther Lake, the "substate_requirements" attribute in the 
newer platforms will show only the requirements of s0ix blockers instead 
of every substate status register. In order to support these two mutual 
exclusive features, additional fields have been added to pmc_dev_info 
struct. This change would not change the functionality of intel_pmc_core 
driver in Arrow Lake platforms.

Thanks for the suggestion, I will add this information to the changelog 
of next version.

Thanks!

Xi

>
> - Russell Haley
>

  reply	other threads:[~2025-09-05 18:43 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-15 22:45 [PATCH v3 0/6] Enable SSRAM support in PTL and LNL Xi Pardee
2025-08-15 22:45 ` [PATCH v3 1/6] platform/x86:intel/pmc: Enable SSRAM support for Lunar Lake Xi Pardee
2025-08-15 22:46 ` [PATCH v3 2/6] platform/x86:intel/pmc: Move telemetry endpoint register handling Xi Pardee
2025-08-15 22:46 ` [PATCH v3 3/6] platform/x86:intel/pmc: Improve function to show substate header Xi Pardee
2025-08-28 13:09   ` Ilpo Järvinen
2025-09-05 16:50     ` Xi Pardee
2025-08-15 22:46 ` [PATCH v3 4/6] platform/x86:intel/pmc: Show substate requirement for S0ix blockers Xi Pardee
2025-08-28 13:06   ` Ilpo Järvinen
2025-09-05 17:31     ` Xi Pardee
2025-09-01 23:52   ` Russell Haley
2025-09-05 18:43     ` Xi Pardee [this message]
2025-08-15 22:46 ` [PATCH v3 5/6] platform/x86:intel/pmc: Show device and function number Xi Pardee
2025-08-28 13:56   ` Ilpo Järvinen
2025-09-07 21:57     ` Xi Pardee
2025-09-08 11:03       ` Ilpo Järvinen
2025-09-11 18:32         ` Xi Pardee
2025-08-15 22:46 ` [PATCH v3 6/6] platform/x86:intel/pmc: Enable SSRAM support for Panther Lake Xi Pardee

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