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([2001:b07:6468:f312:c8dd:75d4:99ab:290a]) by smtp.googlemail.com with ESMTPSA id a1sm2618971wrf.42.2022.01.20.03.18.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Jan 2022 03:18:12 -0800 (PST) Message-ID: <771780a3-39a7-f87e-4b5b-45cf95b3896a@redhat.com> Date: Thu, 20 Jan 2022 12:18:04 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.4.0 Subject: Re: [PATCH v2 5/7] kvm/riscv: rework guest entry logic Content-Language: en-US To: Mark Rutland , linux-kernel@vger.kernel.org Cc: aleksandar.qemu.devel@gmail.com, alexandru.elisei@arm.com, anup.patel@wdc.com, aou@eecs.berkeley.edu, atish.patra@wdc.com, borntraeger@linux.ibm.com, bp@alien8.de, catalin.marinas@arm.com, chenhuacai@kernel.org, dave.hansen@linux.intel.com, frankja@linux.ibm.com, frederic@kernel.org, gor@linux.ibm.com, hca@linux.ibm.com, james.morse@arm.com, jmattson@google.com, joro@8bytes.org, luto@kernel.org, maz@kernel.org, mingo@redhat.com, mpe@ellerman.id.au, nsaenzju@redhat.com, palmer@dabbelt.com, paulmck@kernel.org, paul.walmsley@sifive.com, peterz@infradead.org, seanjc@google.com, suzuki.poulose@arm.com, svens@linux.ibm.com, tglx@linutronix.de, tsbogend@alpha.franken.de, vkuznets@redhat.com, wanpengli@tencent.com, will@kernel.org References: <20220119105854.3160683-1-mark.rutland@arm.com> <20220119105854.3160683-6-mark.rutland@arm.com> From: Paolo Bonzini In-Reply-To: <20220119105854.3160683-6-mark.rutland@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 1/19/22 11:58, Mark Rutland wrote: > + * There's no barrier which ensures that pending interrupts are > + * recognised, so we just hope that the CPU takes any pending > + * interrupts between the enable and disable. > */ > local_irq_enable(); > + local_irq_disable(); > This should be the required architectural behavior: "a CSR access is performed after the execution of any prior instructions in program order whose behavior modifies or is modified by the CSR state and before the execution of any subsequent instructions in program order whose behavior modifies or is modified by the CSR state" (Zicsr spec, paragraph "CSR Access Ordering", available at https://www.five-embeddev.com/riscv-isa-manual/latest/csr.html#csrinsts). Paolo