From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757799AbcEEQOO (ORCPT ); Thu, 5 May 2016 12:14:14 -0400 Received: from mail-gw2-out.broadcom.com ([216.31.210.63]:27694 "EHLO mail-gw2-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757772AbcEEQOL (ORCPT ); Thu, 5 May 2016 12:14:11 -0400 X-IronPort-AV: E=Sophos;i="5.24,582,1455004800"; d="scan'208";a="94775933" Subject: Re: [PATCH v2] irqchip/gic-v2m: Add workaround for Broadcom NS2 GICv2m erratum To: Marc Zyngier , Thomas Gleixner , Jason Cooper References: <1462405635-27864-1-git-send-email-ray.jui@broadcom.com> <1462405635-27864-2-git-send-email-ray.jui@broadcom.com> <572AF86A.1090000@arm.com> Cc: linux-kernel@vger.kernel.org, bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, Alex Barba From: Ray Jui Message-ID: <7724bb0f-9b0e-ea4c-ea87-c462adac1fe9@broadcom.com> Date: Thu, 5 May 2016 09:14:07 -0700 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:45.0) Gecko/20100101 Thunderbird/45.1 MIME-Version: 1.0 In-Reply-To: <572AF86A.1090000@arm.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 5/5/2016 12:38 AM, Marc Zyngier wrote: > On 05/05/16 00:47, Ray Jui wrote: >> Alex Barba discovered Broadcom NS2 GICv2m >> implementation has an erratum where the MSI data needs to be the SPI >> number subtracted by an offset of 32, for the correct MSI interrupt >> to be triggered. >> >> Here we are adding the workaround based on readings from the MSI_IIDR >> register, which contains a value unique to Broadcom NS2 GICv2m >> >> Reported-by: Alex Barba >> Signed-off-by: Ray Jui >> --- >> drivers/irqchip/irq-gic-v2m.c | 17 +++++++++++++++-- >> 1 file changed, 15 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/irqchip/irq-gic-v2m.c b/drivers/irqchip/irq-gic-v2m.c >> index 28f047c..4c89e27 100644 >> --- a/drivers/irqchip/irq-gic-v2m.c >> +++ b/drivers/irqchip/irq-gic-v2m.c >> @@ -49,6 +49,9 @@ >> /* APM X-Gene with GICv2m MSI_IIDR register value */ >> #define XGENE_GICV2M_MSI_IIDR 0x06000170 >> >> +/* Broadcom NS2 GICv2m MSI_IIDR register value */ >> +#define BCM_NS2_GICV2M_MSI_IIDR 0x0000013f >> + >> /* List of flags for specific v2m implementation */ >> #define GICV2M_NEEDS_SPI_OFFSET 0x00000001 >> >> @@ -62,6 +65,7 @@ struct v2m_data { >> void __iomem *base; /* GICv2m virt address */ >> u32 spi_start; /* The SPI number that MSIs start */ >> u32 nr_spis; /* The number of SPIs for MSIs */ >> + u32 spi_offset; /* offset to be subtracted from SPI number */ >> unsigned long *bm; /* MSI vector bitmap */ >> u32 flags; /* v2m flags for specific implementation */ >> }; >> @@ -102,7 +106,7 @@ static void gicv2m_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) >> msg->data = data->hwirq; >> >> if (v2m->flags & GICV2M_NEEDS_SPI_OFFSET) >> - msg->data -= v2m->spi_start; >> + msg->data -= v2m->spi_offset; >> } >> >> static struct irq_chip gicv2m_irq_chip = { >> @@ -340,9 +344,18 @@ static int __init gicv2m_init_one(struct fwnode_handle *fwnode, >> * different from the standard GICv2m implementation where >> * the MSI data is the absolute value within the range from >> * spi_start to (spi_start + num_spis). >> + * >> + * Broadom NS2 GICv2m implementation has an erratum where the MSI data >> + * is 'spi_number - 32' >> */ >> - if (readl_relaxed(v2m->base + V2M_MSI_IIDR) == XGENE_GICV2M_MSI_IIDR) >> + if (readl_relaxed(v2m->base + V2M_MSI_IIDR) == XGENE_GICV2M_MSI_IIDR) { >> + v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; >> + v2m->spi_offset = v2m->spi_start; >> + } else if (readl_relaxed(v2m->base + V2M_MSI_IIDR) == >> + BCM_NS2_GICV2M_MSI_IIDR) { >> v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; >> + v2m->spi_offset = 32; >> + } > > Can we make this a bit less ugly? > > switch (readl_relaxed(v2m->base + V2M_MSI_IIDR)) { > case XGENE_GICV2M_MSI_IIDR: > v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; > v2m->spi_offset = v2m->spi_start; > break; > case BCM_NS2_GICV2M_MSI_IIDR: > v2m->flags |= GICV2M_NEEDS_SPI_OFFSET; > v2m->spi_offset = 32; > break; > } Okay will do that! > > Thanks, > > M. > Thanks, Ray