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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: KayIHOsA0clWquL9Y6-ThmyNYBLJU4EZ X-Authority-Analysis: v=2.4 cv=deGwG3Xe c=1 sm=1 tr=0 ts=6a268af9 cx=c_pps a=mPf7EqFMSY9/WdsSgAYMbA==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=cTwmTnRGAAAA:8 a=Ut5rIDj74-HqtMDnOCEA:9 a=QEXdDO2ut3YA:10 a=dawVfQjAaf238kedN5IG:22 a=GUWCSGlMWfG-xDt5EnV5:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA4MDA4NyBTYWx0ZWRfX0tOopXpQQUZi OjYhlXGmwX92AdkT2V55PcmpIEHM3uF07/Vi4AxSNcTVs8adCHupjUqz9EtDlKh0ydy5BtD7TJl /YKhiD8et6HTy61j+ZHJFe57D0L32QCOlcmDmsWl/R2phAp/n5JKzexpX34CH4krK47AwmgDRs6 WeMNyft/gxwIDmEk0WwpxR5gGOKfA/+q0Og9qvi0H3oopSiapZqM0tCDTlxrT4b8qTQPwJYj9/R iWhBxgrUKt4bUTMptUOGbybf4/Cay2Dn1HsBGn6M75KDfGCQ9t/+wTTt11IMvQ9Lw3CAXpcxD1b Q21ffXK6sxSCHSBrMROxL67GMiuQxpBH66TuuUmwsfhQVkuMF5Kq4rKu1Gj6ZrQTe7D7+nR5G7a 7V0IXVv4pFpbr7oEmzsUbgZnbl0ncIZ5aPlSablX9pSUNuMUu/9gsbeUwP0Ib25BLM8+47tDQ/G BkfQDi8wTVt7MBlzd6w== X-Proofpoint-GUID: KayIHOsA0clWquL9Y6-ThmyNYBLJU4EZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-08_02,2026-06-05_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 phishscore=0 impostorscore=0 priorityscore=1501 bulkscore=0 adultscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606080087 On 6/2/26 6:49 AM, Herman van Hazendonk wrote: > The PLL4 L-register read in probe was used to select between the 393 MHz > and 492 MHz frequency plans without checking whether the underlying > regmap operation succeeded; a silent failure would leave the rcg > structures pointing at whatever default they had at startup (the 393 > MHz plan) and the chosen plan could be wrong for the running PLL, > producing incorrect audio clock rates without any diagnostic. > > The unconditional write to register 0xc4 that arms the LPASS Primary > PLL mux on PLL4 had the same problem: a bus-level failure would leave > the mux at its default (PXO) and every downstream LCC clock would be > sourced from the wrong parent without a warning. > > Use dev_err_probe() in both spots so the error is surfaced (and the > deferred-probe state machine handles the EPROBE_DEFER-from-bus-arbiter > case correctly) and the driver does not bind in a known-bad > configuration. > > Signed-off-by: Herman van Hazendonk > --- Can this happen in practice? LCC seems to be a device on the MMIO bus.. Konrad