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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f6744c923sm3959387b3a.52.2026.04.15.22.42.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Apr 2026 22:42:44 -0700 (PDT) Message-ID: <778a826b-918d-4f7c-95a9-1cdb013618d8@oss.qualcomm.com> Date: Thu, 16 Apr 2026 13:42:40 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 04/12] coresight: etm4x: exclude ss_status from drvdata->config To: Yeoreum Yun , coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com References: <20260415165528.3369607-1-yeoreum.yun@arm.com> <20260415165528.3369607-5-yeoreum.yun@arm.com> Content-Language: en-US From: Jie Gan In-Reply-To: <20260415165528.3369607-5-yeoreum.yun@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: yYYC3IPmo_hDFC1IEON92k56QJTYMFH4 X-Authority-Analysis: v=2.4 cv=HMjz0Itv c=1 sm=1 tr=0 ts=69e076d6 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=7CQSdrXTAAAA:8 a=KKAkSRfTAAAA:8 a=LI8sGVgq26al4nlOv0QA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 a=a-qgeE7W1pNrGK8U0ZQC:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: yYYC3IPmo_hDFC1IEON92k56QJTYMFH4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE2MDA1MSBTYWx0ZWRfXwaRzrNhawlc+ KG3v3Pl5Hc9jUCWHO/k30D3Ww7rgXEagf4w9FHWyezLZBIimU81fcbEndfYqKYRT74psvsY1xgp BjkjhoHH2ocG8WV22dtVKYJWLVNq2AezrotxPwN8BHedU5mMN/vSaYPNHeUAuCytrpRfc8NIcTg LOK044/cU5UhbHL40IEqV+v9xL5nbavCpPwV/hmQRZMyszRZ0LkqZKiBYCS+IUbcQiBpNWlOD+6 S9OLh6xPdhL76lY5YjaX9yFnJlK0mq0y1Q7uf8rEC2JYU2rGJCBWitAfmhpZMRW2J/8RLstO+en XxqINVkPEI1Ov7V4U/nvXt2Hp5eKp8/uT8GOVdkCtPAeUoTFEXVIUhkz5fdWWE0UDZ+Kw6SbXVo uLwSxoMSAvY+BadnKlGlYqcCGRdRm/55wDnk9xEVR64MI3BLcjOEzElP9eJttlmVn7MDn91Q+nO 8HvmziguoLjBEaUj5yQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-16_01,2026-04-13_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 malwarescore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604160051 On 4/16/2026 12:55 AM, Yeoreum Yun wrote: > The purpose of TRCSSCSRn register is to show status of > the corresponding Single-shot Comparator Control and input supports. > That means writable field's purpose for reset or restore from idle status > not for configuration. > > Therefore, exclude ss_status from drvdata->config, move it to etm4x_caps > and rename it to ss_smp. > > This includes remove TRCSSCRn from configurable item and > remove saving in etm4_disable_hw(). > > Signed-off-by: Yeoreum Yun > --- > .../hwtracing/coresight/coresight-etm4x-cfg.c | 1 - > .../coresight/coresight-etm4x-core.c | 19 ++++++------------- > .../coresight/coresight-etm4x-sysfs.c | 7 ++----- > drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++++++- > 4 files changed, 14 insertions(+), 20 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > index c302072b293a..d14d7c8a23e5 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c > @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *drvdata, > off_mask = (offset & GENMASK(11, 5)); > do { > CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask); > - CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask); > CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask); > } while (0); > } else if ((offset >= TRCCIDCVRn(0)) && (offset <= TRCVMIDCVRn(7))) { > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index b2b092a76eb5..f55338a4989d 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -91,7 +91,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) > const struct etmv4_caps *caps = &drvdata->caps; > > return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp && > - (drvdata->config.ss_status[n] & TRCSSCSRn_PC); > + (caps->ss_cmp[n] & TRCSSCSRn_PC); > } > > u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) > @@ -573,11 +573,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); > > for (i = 0; i < caps->nr_ss_cmp; i++) { > - /* always clear status bit on restart if using single-shot */ > - if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) > - config->ss_status[i] &= ~TRCSSCSRn_STATUS; > etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); > - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); > + /* always clear status and pending bits on restart if using single-shot */ > + etm4x_relaxed_write32(csa, 0x0, TRCSSCSRn(i)); > if (etm4x_sspcicrn_present(drvdata, i)) > etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); > } > @@ -1055,12 +1053,6 @@ static void etm4_disable_hw(struct etmv4_drvdata *drvdata) > > etm4_disable_trace_unit(drvdata); > > - /* read the status of the single shot comparators */ > - for (i = 0; i < caps->nr_ss_cmp; i++) { > - config->ss_status[i] = > - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); > - } > - > /* read back the current counter values */ > for (i = 0; i < caps->nr_cntr; i++) { > config->cntr_val[i] = > @@ -1503,8 +1495,9 @@ static void etm4_init_arch_data(void *info) > */ > caps->nr_ss_cmp = FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); > for (i = 0; i < caps->nr_ss_cmp; i++) { > - drvdata->config.ss_status[i] = > - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); > + caps->ss_cmp[i] = etm4x_relaxed_read32(csa, TRCSSCSRn(i)); > + caps->ss_cmp[i] &= (TRCSSCSRn_PC | TRCSSCSRn_DV | > + TRCSSCSRn_DA | TRCSSCSRn_INST); Just re-go through this patch and had a question here: I’m not sure whether this new change should be documented in the ABI, given that the TRCSSCSRn_STATUS bit is masked. In my opinion, this change breaks the existing ABI description. Description from the ABI document: What: /sys/bus/coresight/devices/etm/sshot_status Date: December 2019 KernelVersion: 5.5 Contact: Mathieu Poirier Description: (Read) Print the current value of the selected single shot status register. Thanks, Jie > } > /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ > caps->numcidc = FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > index 8bd28e71d4c9..5e26c2ec8f7b 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c > @@ -1829,8 +1829,6 @@ static ssize_t sshot_ctrl_store(struct device *dev, > raw_spin_lock(&drvdata->spinlock); > idx = config->ss_idx; > config->ss_ctrl[idx] = FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val); > - /* must clear bit 31 in related status register on programming */ > - config->ss_status[idx] &= ~TRCSSCSRn_STATUS; > raw_spin_unlock(&drvdata->spinlock); > return size; > } > @@ -1841,10 +1839,11 @@ static ssize_t sshot_status_show(struct device *dev, > { > unsigned long val; > struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); > + const struct etmv4_caps *caps = &drvdata->caps; > struct etmv4_config *config = &drvdata->config; > > raw_spin_lock(&drvdata->spinlock); > - val = config->ss_status[config->ss_idx]; > + val = caps->ss_cmp[config->ss_idx]; > raw_spin_unlock(&drvdata->spinlock); > return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); > } > @@ -1879,8 +1878,6 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, > raw_spin_lock(&drvdata->spinlock); > idx = config->ss_idx; > config->ss_pe_cmp[idx] = FIELD_PREP(TRCSSPCICRn_PC_MASK, val); > - /* must clear bit 31 in related status register on programming */ > - config->ss_status[idx] &= ~TRCSSCSRn_STATUS; > raw_spin_unlock(&drvdata->spinlock); > return size; > } > diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h > index 8168676f2945..db56c4414873 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x.h > +++ b/drivers/hwtracing/coresight/coresight-etm4x.h > @@ -213,6 +213,7 @@ > #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8) > > #define TRCSSCSRn_STATUS BIT(31) > +#define TRCSSCSRn_PENDING BIT(30) > #define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0) > > #define TRCSSPCICRn_PC_MASK GENMASK(7, 0) > @@ -729,6 +730,9 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx) > #define ETM_DEFAULT_ADDR_COMP 0 > > #define TRCSSCSRn_PC BIT(3) > +#define TRCSSCSRn_DV BIT(2) > +#define TRCSSCSRn_DA BIT(1) > +#define TRCSSCSRn_INST BIT(0) > > /* PowerDown Control Register bits */ > #define TRCPDCR_PU BIT(3) > @@ -861,6 +865,7 @@ enum etm_impdef_type { > * @lpoverride: If the implementation can support low-power state over. > * @skip_power_up: Indicates if an implementation can skip powering up > * the trace unit. > + * @ss_cmp: Indicates supported single-shot comparators. > */ > struct etmv4_caps { > u8 nr_pe; > @@ -899,6 +904,7 @@ struct etmv4_caps { > bool atbtrig : 1; > bool lpoverride : 1; > bool skip_power_up : 1; > + u32 ss_cmp[ETM_MAX_SS_CMP]; > }; > > /** > @@ -977,7 +983,6 @@ struct etmv4_config { > u32 res_ctrl[ETM_MAX_RES_SEL]; /* TRCRSCTLRn */ > u8 ss_idx; > u32 ss_ctrl[ETM_MAX_SS_CMP]; > - u32 ss_status[ETM_MAX_SS_CMP]; > u32 ss_pe_cmp[ETM_MAX_SS_CMP]; > u8 addr_idx; > u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];