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From: Andrew Lunn <andrew@lunn.ch>
To: javen <javen_xu@realsil.com.cn>
Cc: hkallweit1@gmail.com, nic_swsd@realtek.com,
	andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,
	kuba@kernel.org, pabeni@redhat.com, horms@kernel.org,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH net-next v1 1/3] r8169: make PHY OCP access safe in atomic context
Date: Mon, 9 Nov 2026 21:47:54 +0100	[thread overview]
Message-ID: <7791e7b5-fdc8-4c8c-ab5b-dcc7d7a6506a@lunn.ch> (raw)
In-Reply-To: <20261109023022.770-2-javen_xu@realsil.com.cn>

On Mon, Nov 09, 2026 at 10:30:20AM +0800, javen wrote:
> From: Javen Xu <javen_xu@realsil.com.cn>
> 
> r8168_phy_ocp_read() and r8168_phy_ocp_write() wait for the GPHY_OCP
> handshake with rtl_loop_wait(), which may sleep (fsleep(25)). Upcoming
> PTP support for RTL8127A accesses the PTP block through the same PHY
> OCP interface from atomic context (spinlock held, NAPI RX path), and
> concurrently with phylib MDIO accesses.
> 
> Busy-wait for the handshake with readl_poll_timeout_atomic() instead,
> keeping the previous maximum wait time of 250us, and serialize the
> GPHY_OCP register accesses with a new spinlock.

There are many drivers which need to access PHY registers via blocking
MDIO accesses. Why is this driver different?

	Andrew

  reply	other threads:[~2026-11-09 20:48 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-09  2:30 [PATCH net-next v1 0/3] r8169: add PTP support for RTL8127a javen
2026-11-09  2:30 ` [PATCH net-next v1 1/3] r8169: make PHY OCP access safe in atomic context javen
2026-11-09 20:47   ` Andrew Lunn [this message]
2026-11-09  2:30 ` [PATCH net-next v1 2/3] r8169: add PTP hardware clock support for RTL8127a javen
2026-11-09 20:51   ` Andrew Lunn
2026-11-09  2:30 ` [PATCH net-next v1 3/3] r8169: add hardware timestamping " javen

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