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Fri, 22 May 2026 09:07:56 -0700 (PDT) Message-ID: <779f2680-2c67-4bbd-9576-bde8e83d111d@linaro.org> Date: Fri, 22 May 2026 19:07:53 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 04/28] mtd: spi-nor: swp: Improve locking user experience To: Miquel Raynal Cc: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Richard Weinberger , Vignesh Raghavendra , Jonathan Corbet , Shuah Khan , Sean Anderson , Thomas Petazzoni , Steam Lin , linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, stable@kernel.org References: <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-0-93453e1a9597@bootlin.com> <20260507-winbond-v6-18-rc1-spi-nor-swp-v5-4-93453e1a9597@bootlin.com> <9432f07f-3724-4257-b6ab-84721e619f78@linaro.org> <875x4fphgr.fsf@bootlin.com> Content-Language: en-US From: Tudor Ambarus In-Reply-To: <875x4fphgr.fsf@bootlin.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 5/22/26 6:55 PM, Miquel Raynal wrote: > On 22/05/2026 at 12:10:45 +03, Tudor Ambarus wrote: > >> On 5/7/26 7:46 PM, Miquel Raynal wrote: >>> Fixes: 3dd8012a8eeb ("mtd: spi-nor: add TB (Top/Bottom) protect support") >>> Cc: stable@kernel.org >> Fixes shall be the first patches in the set. > > Technically speaking all four first patches are fixes, except I don't > ask the first one to be backported. The reason why we ask fixes to be > first in the series is because we want them to be as independent as > possible from previous cleanups/changes. Here each four first patch are > targeting completely different places and should not interact with each > other. Anyway, I will re-shuffle the patches. you don't need to resend just for that I think. Pratyush or Michael can re-shuffle when applying. > > As for Sashiko's feedback, the AI raises the same point as our previous > discussion: the QE bit handling is really bad, and I am working on I forgot what we talked about, sorry. > improving this, in another series which waits for this one to land. > > However the other warning it raises is IMO wrong: mixed-modes chips > (either read or write working in quad mode, and the other in single that's good to know, thanks. It assures people that the AI feedback was considered. > mode) should enable their QE bit anyway. Please raise a warning if you > think this assumption is wrong. Not sure if I'll be able to allocate time to review it. No blockers from my side. Cheers, ta