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Mon, 7 Oct 2024 17:35:44 -0500 Message-ID: <77ad50fa-5c94-a93b-a123-48f653291f51@amd.com> Date: Mon, 7 Oct 2024 15:35:44 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [PATCH V3 06/11] accel/amdxdna: Add GEM buffer object management Content-Language: en-US To: Jeffrey Hugo , , CC: , , , , References: <20240911180604.1834434-1-lizhi.hou@amd.com> <20240911180604.1834434-7-lizhi.hou@amd.com> From: Lizhi Hou In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA52:EE_|PH8PR12MB6916:EE_ X-MS-Office365-Filtering-Correlation-Id: 778cce66-e192-43e5-d52b-08dce7206302 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Oct 2024 22:35:46.4930 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 778cce66-e192-43e5-d52b-08dce7206302 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA52.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6916 On 10/4/24 10:56, Jeffrey Hugo wrote: > On 9/11/2024 12:05 PM, Lizhi Hou wrote: >> +/** >> + * struct amdxdna_drm_create_bo - Create a buffer object. >> + * @flags: Buffer flags. MBZ. >> + * @type: Buffer type. >> + * @pad1: MBZ. >> + * @vaddr: User VA of buffer if applied. MBZ. >> + * @size: Size in bytes. >> + * @handle: Returned DRM buffer object handle. >> + * @pad2: MBZ. >> + */ >> +struct amdxdna_drm_create_bo { >> +    __u64    flags; >> +    __u32    type; >> +    __u32    pad1; >> +    __u64    vaddr; >> +    __u64    size; >> +    __u32    handle; >> +    __u32    pad2; >> +}; > > Why not eliminate both padding fields by either moving "handle" up, or > "type" down? Ok. I will change this. Thanks, Lizhi