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Thu, 22 Jan 2026 10:14:31 -0600 Received: from [128.247.81.19] (uda0506412.dhcp.ti.com [128.247.81.19]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 60MGEVNb827155; Thu, 22 Jan 2026 10:14:31 -0600 Message-ID: <77b3b869-558f-4854-95b0-57980be28032@ti.com> Date: Thu, 22 Jan 2026 10:14:31 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: dts: ti: k3-am62l: support cpufreq To: Dhruva Gole , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Bryan Brattlof , Viresh Kumar References: <20260122-am62l-dt-cpufreq-v1-1-fabcc15e25fa@ti.com> Content-Language: en-US From: Kendall Willis In-Reply-To: <20260122-am62l-dt-cpufreq-v1-1-fabcc15e25fa@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF000099DF:EE_|CO6PR10MB5538:EE_ X-MS-Office365-Filtering-Correlation-Id: b8c11caf-e78c-48b0-b189-08de59d15511 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|1800799024|376014; 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X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jan 2026 16:14:34.2401 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b8c11caf-e78c-48b0-b189-08de59d15511 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF000099DF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR10MB5538 On 1/22/26 04:49, Dhruva Gole wrote: > Enable CPUFreq support for AM62L SoC by adding the relevant OPP efuse table > syscon to k3-am62l-wakeup.dtsi for speed grade detection. > > Add the operating-points-v2 table with CPU frequency steps from 200MHz to > 1.25GHz to k3-am62l3.dtsi > > Configure CPU clocks to reference the SCMI clock controller for frequency > scaling > > This enables proper CPU frequency scaling capabilities for the AM62L SoC > using the ARM SCMI protocol to interact with the power management firmware. > > Signed-off-by: Dhruva Gole Reviewed-by: Kendall Willis Best, Kendall Willis