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Mon, 18 Aug 2025 00:17:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEQzDZnDrRPt9e9ar4NcGlKQx/v15yiS7nW8hWVOCiahtj0oNaVAIJtchO0QDQCqoEqEh/UUQ== X-Received: by 2002:a17:902:f645:b0:240:86b2:ae9c with SMTP id d9443c01a7336-2446bdad87bmr122769485ad.14.1755501443427; Mon, 18 Aug 2025 00:17:23 -0700 (PDT) Received: from [192.168.1.4] ([106.222.229.157]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2446ca9dbfdsm71325165ad.19.2025.08.18.00.17.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 Aug 2025 00:17:23 -0700 (PDT) Message-ID: <77db4861-4868-4110-8c31-eb2045ddbf4b@oss.qualcomm.com> Date: Mon, 18 Aug 2025 12:47:17 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU To: Dmitry Baryshkov , Konrad Dybcio Cc: Neil Armstrong , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org References: <20250725-topic-x1e80100-gpu-bwvote-v2-1-58d2fbb6a127@linaro.org> <33442cc4-a205-46a8-a2b8-5c85c236c8d4@oss.qualcomm.com> <269506b6-f51b-45cc-b7cc-7ad0e5ceea47@linaro.org> <1727374d-0461-4442-ab35-9acb8ef7f666@oss.qualcomm.com> From: Akhil P Oommen Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=MJ9gmNZl c=1 sm=1 tr=0 ts=68a2d385 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=9Q8gPALlkHEzzDxkdHlyxw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=tT0-4YtFDMztOtjXKeIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: ITkovWhpHZqXfLm7_zWqTx6p269y09mi X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE2MDAzMSBTYWx0ZWRfX5ri4BfLE8Vy0 hX4EIaxqbmmgqfEhd/s/ffkFKas5HDSGld0ad8r2VM/g8PaSnxLp4cLviEUyyOECcwhXik7i6D0 niQNQedbL0lWu4AwPjKAJ3HpjC1jv5I8N3lHy9YrDcMi/VLIcqkSXHTbQNcDfvps2APFmzMzfDR i+j66Q/izCApzJmzOyAh4LKb4rI9E4nKFtUJtTsnFwGWqssHFSJ4M2Rxc2edf541uQqjQXlJrwl nE/fmNiTvZHybIOd0KRwz31xJDxT5EsWN2wrkhIEhCPL6CW4fTZkAMWevECSWDJ5KhxFRUAUTdZ cjd0exGz/kgVh4skcfbM6hsp8AUaQQEvJTqF7XpLgOWkrPGkKGSmziDIvOZFwjh2O6vhlJfC9fJ dHVdXGWv X-Proofpoint-GUID: ITkovWhpHZqXfLm7_zWqTx6p269y09mi X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-18_03,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 phishscore=0 bulkscore=0 malwarescore=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508160031 On 8/16/2025 3:45 AM, Dmitry Baryshkov wrote: > On Thu, Aug 14, 2025 at 07:52:13PM +0200, Konrad Dybcio wrote: >> On 8/14/25 6:38 PM, Akhil P Oommen wrote: >>> On 8/14/2025 7:56 PM, Neil Armstrong wrote: >>>> Hi, >>>> >>>> On 14/08/2025 13:22, Konrad Dybcio wrote: >>>>> On 8/14/25 1:21 PM, Konrad Dybcio wrote: >>>>>> On 7/31/25 12:19 PM, Konrad Dybcio wrote: >>>>>>> On 7/25/25 10:35 AM, Neil Armstrong wrote: >>>>>>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth >>>>>>>> along >>>>>>>> the Frequency and Power Domain level, but by default we leave the >>>>>>>> OPP core scale the interconnect ddr path. >>>>>>>> >>>>>>>> Declare the Bus Control Modules (BCMs) and the corresponding >>>>>>>> parameters >>>>>>>> in the GPU info struct to allow the GMU to vote for the bandwidth. >>>>>>>> >>>>>>>> Reviewed-by: Dmitry Baryshkov >>>>>>>> Signed-off-by: Neil Armstrong >>>>>>>> --- >>>>>>>> Changes in v2: >>>>>>>> - Used proper ACV perfmode bit/freq >>>>>>>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100- >>>>>>>> gpu-bwvote-v1-1-946619b0f73a@linaro.org >>>>>>>> --- >>>>>>>>   drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++ >>>>>>>>   1 file changed, 11 insertions(+) >>>>>>>> >>>>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/ >>>>>>>> gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>> index >>>>>>>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644 >>>>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>>>>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = { >>>>>>>>               .pwrup_reglist = &a7xx_pwrup_reglist, >>>>>>>>               .gmu_chipid = 0x7050001, >>>>>>>>               .gmu_cgc_mode = 0x00020202, >>>>>>>> +            .bcms = (const struct a6xx_bcm[]) { >>>>>>>> +                { .name = "SH0", .buswidth = 16 }, >>>>>>>> +                { .name = "MC0", .buswidth = 4 }, >>>>>>>> +                { >>>>>>>> +                    .name = "ACV", >>>>>>>> +                    .fixed = true, >>>>>>>> +                    .perfmode = BIT(3), >>>>>>>> +                    .perfmode_bw = 16500000, >>>>>>> >>>>>>> Reviewed-by: Konrad Dybcio >>>>>> >>>>>> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2) >>> >>> You are right that BIT(2) is GPU specific, but that support was >>> commercialized from A7XX_GEN3. Anyway, the Win KMD uses BIT(2), so lets >>> use that in Linux too. >>> >>> I know some docs show BIT(2) support, but lets not bring in untested >>> configurations. >> >> Eh, then let's get the docs fixed if you don't trust them because we can't >> work like that.. >> >> FWIW this is information from per-platform RPMh cmd-db data > > If it comes from cmd-db, then we should be requesting it from the cmd-db > driver rather than hardcoding it here. Not really. This should be under the control of GPU driver. BIT(3) is correct for X1E. -Akhil. >