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Thu, 08 Jan 2026 10:19:58 -0800 (PST) Message-ID: <77f9a001-7f0a-4c29-abcb-501e875da117@sifive.com> Date: Thu, 8 Jan 2026 12:19:56 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 10/11] riscv: dts: spacemit: add initial device tree of SpacemiT K3 SoC To: Guodong Xu Cc: Paul Walmsley , Conor Dooley , Heinrich Schuchardt , Kevin Meng Zhang , Andrew Jones , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, spacemit@lists.linux.dev, linux-serial@vger.kernel.org, Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yixun Lan , Daniel Lezcano , Thomas Gleixner , Anup Patel , Greg Kroah-Hartman , Jiri Slaby , Lubomir Rintel , Yangyu Chen References: <20260108-k3-basic-dt-v3-0-ed99eb4c3ad3@riscstar.com> <20260108-k3-basic-dt-v3-10-ed99eb4c3ad3@riscstar.com> From: Samuel Holland Content-Language: en-US In-Reply-To: <20260108-k3-basic-dt-v3-10-ed99eb4c3ad3@riscstar.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 2026-01-08 6:26 AM, Guodong Xu wrote: > SpacemiT K3 is equipped with 8 X100 cores, which are RVA23 compliant. > Add nodes of uarts, timer and interrupt-controllers. > > Signed-off-by: Guodong Xu > --- > v3: Remove "supm" from the riscv,isa-extensions list. > v2: Remove aliases from k3.dtsi, they should be in board DTS. > Updated riscv,isa-extensions with new extensions from the extensions.yaml > --- > arch/riscv/boot/dts/spacemit/k3.dtsi | 548 +++++++++++++++++++++++++++++++++++ > 1 file changed, 548 insertions(+) > > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > new file mode 100644 > index 0000000000000000000000000000000000000000..be9335fba32cb9e81915b2b91cf08c55a5e96809 > --- /dev/null > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > [...] > + > + simsic: interrupt-controller@e0400000 { > + compatible = "spacemit,k3-imsics","riscv,imsics"; style: missing space after comma > + reg = <0x0 0xe0400000 0x0 0x00200000>; > + interrupt-controller; > + #interrupt-cells = <0>; > + msi-controller; > + #msi-cells = <0>; > + interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, > + <&cpu2_intc 9>, <&cpu3_intc 9>, > + <&cpu4_intc 9>, <&cpu5_intc 9>, > + <&cpu6_intc 9>, <&cpu7_intc 9>; > + riscv,num-ids = <511>; > + riscv,num-guest-ids = <511>; > + riscv,hart-index-bits = <4>; > + riscv,guest-index-bits = <6>; > + }; > + > + saplic: interrupt-controller@e0804000 { > + compatible = "spacemit,k3-aplic", "riscv,aplic"; > + reg = <0x0 0xe0804000 0x0 0x4000>; > + msi-parent = <&simsic>; > + #interrupt-cells = <2>; > + interrupt-controller; > + riscv,num-sources = <512>; > + }; Does the chip also have M-mode IMSIC and APLIC instances? Those need to be represented in the devicetree as well, for M-mode firmware to access them, just like the CLINT below. Regards, Samuel > + > + clint: timer@e081c000 { > + compatible = "spacemit,k3-clint", "sifive,clint0"; > + reg = <0x0 0xe081c000 0x0 0x0004000>; > + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, > + <&cpu1_intc 3>, <&cpu1_intc 7>, > + <&cpu2_intc 3>, <&cpu2_intc 7>, > + <&cpu3_intc 3>, <&cpu3_intc 7>, > + <&cpu4_intc 3>, <&cpu4_intc 7>, > + <&cpu5_intc 3>, <&cpu5_intc 7>, > + <&cpu6_intc 3>, <&cpu6_intc 7>, > + <&cpu7_intc 3>, <&cpu7_intc 7>; > + }; > + }; > +}; >