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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CY4PEPF0000FCC2.mail.protection.outlook.com (10.167.242.104) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.113.7 via Frontend Transport; Sun, 7 Jun 2026 11:07:59 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 7 Jun 2026 04:07:49 -0700 Received: from [10.125.203.115] (10.126.230.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Sun, 7 Jun 2026 04:07:43 -0700 Message-ID: <780469a1-1fe4-4985-8253-2d24f3b7cf84@nvidia.com> Date: Sun, 7 Jun 2026 14:07:38 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH net-next 10/15] net/mlx5: LAG, disable both regular and SD LAG on lag_disable_change To: Tariq Toukan , Eric Dumazet , Jakub Kicinski , Paolo Abeni , "Andrew Lunn" , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Mark Bloch , Or Har-Toov , "Edward Srouji" , Simon Horman , Maher Sanalla , Parav Pandit , Kees Cook , Moshe Shemesh , Patrisious Haddad , , , , Gal Pressman References: <20260604114455.434711-1-tariqt@nvidia.com> <20260604114455.434711-11-tariqt@nvidia.com> Content-Language: en-US From: Shay Drori In-Reply-To: <20260604114455.434711-11-tariqt@nvidia.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: rnnvmail202.nvidia.com (10.129.68.7) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000FCC2:EE_|LV2PR12MB5871:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e3b31bd-cc4d-4297-3812-08dec485093d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|7416014|376014|82310400026|22082099003|18002099003|4143699003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: boW9M42mBDzkQv8fC5PPJgoG8REBA+MO/ya2Y5uNHpmeOJotqrTcuRr9lHAwThLkbkE3gNoUTxCLukhg0z3zK88YWQ4zNNZa6/Y2SvVjhtb8QUQyBAQZoi+0VEF+TNQ9+bkdk0C7Zg7t870IeuXim0VPZQHznOTeEjqDcAe0CUSystJAU6R8OYBt0S5HwRniKUf/L3sjSrqYKEtSaqMadFW6hMzIyCZKaLY4hdmCU3GStts/xJa5zkgvXNrddmHjErebyCchQr59uS8EC2D+7+nWa/SUkZiHLfYcnzbmCEF+7UpN3MVYURyBJ3OHL9g1ncc+A5dhgKtazjRKhkGtwdU6uU3rZKuy5XK5eS9yWSQszJY7uZ1iCs96RVI+NPOzc44DdQIFMGtv/Eqmd7AUA3zm3K1TKXiwcSgz3MKOhkcxwQyvuigXZYDM70G7Ofxs1zBSyWNVmDZXlnb7uAp2qm+UhERzNsNM0kHUuoS/qNxfOUV2nFkaeWiMXd6/E5bsjmLjE51fyMK/nYsi1M4APNo9z7oaN9g22Ql4HN1e1Q6XSJq5+zwWFLws3UX81Dvl51oyHM/CQX22FGHU6oF94thqL+oWs1rdhAMlLDQIUkgDHHHSCoB2AGbV6W3Di4/P1PMkjr/Jkcl9FN19dwI7n9apg/bWmfTKMXfXQcA/AKgYO93A89ryT3JBcjuUi9pQizzPHFOvzkdrdEEqopiJEeCQR0LjuMTYfnMyWMRYgAg= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(7416014)(376014)(82310400026)(22082099003)(18002099003)(4143699003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: gMQIm0bb2ww+GT6xqjXYpBTbpeL/5wspHeyNOkj3ftbt3Jjl7f/RBtQGe12kifuduSEL4g1V4Tv7VM06vz0N11B8w2dAR7DQ7TFRov6HXet31nzYK5wyW3ufDgJPzebZTxJyJAe3p4kr0Flv1FOQLXk3x3ZqdL4x/7q+/S1xGzXJoh6iJENxTH9/tx4iK4BCoAGbmC/hRDA9+O8el6ZCjZv4b0n+S3yZdiI3tCgrlHeHSXbOt8iJIjT1tlWM05FlQXLX5f5LHBgxLxpWBUURiTI/BQxcGJLns7Iplc1G2Vv9n/NVURDszvrNqXgbNrICrrhyUVf2sLl9/fTje4+Q6ag9UQUDk7FYKPLqstk1TYoaDHyqQ8TTI3s15bvub71/IoTbXtn9hJv74YsmAKux8U6Cp3oEGZdmyRLTiUgJNcTaYOXEu3x7VNb2NiKKWJDa X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jun 2026 11:07:59.7290 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e3b31bd-cc4d-4297-3812-08dec485093d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000FCC2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5871 On 04/06/2026 14:44, Tariq Toukan wrote: > From: Shay Drory > > Extend mlx5_lag_disable_change() to properly disable both regular LAG > and SD LAG when requested. Each LAG type uses its own devcom component > for locking. > > Use mlx5_sd_get_devcom() helper to retrieve the SD devcom component, > needed for proper locking when disabling SD LAG. > > Signed-off-by: Shay Drory > Reviewed-by: Mark Bloch > Signed-off-by: Tariq Toukan > --- > .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 25 +++++++++++++++++-- > 1 file changed, 23 insertions(+), 2 deletions(-) > > diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c > index e23c1e81b98f..b660253ffc6d 100644 > --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c > +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c > @@ -2494,13 +2494,18 @@ EXPORT_SYMBOL(mlx5_lag_is_shared_fdb); > > void mlx5_lag_disable_change(struct mlx5_core_dev *dev) > { > + struct mlx5_devcom_comp_dev *sd_devcom = mlx5_sd_get_devcom(dev); > + struct mlx5_core_dev *primary; > struct mlx5_lag *ldev; > + struct lag_func *pf; > + int i; > > ldev = mlx5_lag_dev(dev); > if (!ldev) > return; > > - mlx5_devcom_comp_lock(dev->priv.hca_devcom_comp); > + primary = mlx5_sd_get_primary(dev) ?: dev; > + mlx5_devcom_comp_lock(primary->priv.hca_devcom_comp); sashiko.dev says: Could this lockless retrieval of the primary device pointer lead to a use-after-free if the primary device is concurrently unbound? For secondary devices, mlx5_sd_get_primary() reads sd->primary_dev without acquiring a reference count or holding the sd->devcom lock. In a hot-unplug scenario where the primary PF is being unbound: CPU1 (Unbind Primary) mlx5_sd_cleanup() mlx5_devcom_comp_lock(sd->devcom); peer_sd->primary_dev = NULL; // cleared for all secondaries mlx5_devcom_comp_unlock(sd->devcom); // proceeds to free the primary mlx5_core_dev CPU2 (eswitch mode change on secondary PF) mlx5_lag_disable_change() primary = mlx5_sd_get_primary(dev); // reads pointer before CPU1 clears it If CPU2 reads the pointer before CPU1 clears it, wouldn't CPU2 then dereference a freed primary device when calling mlx5_devcom_comp_lock(primary->priv.hca_devcom_comp) shortly after? Should the SD devcom lock be acquired before fetching the primary device to guarantee its valid lifecycle? Added the lock in V2 > mutex_lock(&ldev->lock); > > ldev->mode_changes_in_progress++; > @@ -2512,7 +2517,23 @@ void mlx5_lag_disable_change(struct mlx5_core_dev *dev) > } > > mutex_unlock(&ldev->lock); > - mlx5_devcom_comp_unlock(dev->priv.hca_devcom_comp); > + mlx5_devcom_comp_unlock(primary->priv.hca_devcom_comp); > + > + if (!sd_devcom) > + return; > + > + /* Teardown SD shared FDB for this device's group if active */ > + mlx5_devcom_comp_lock(sd_devcom); > + mutex_lock(&ldev->lock); > + mlx5_lag_for_each(i, 0, ldev, MLX5_LAG_FILTER_ALL) { > + pf = mlx5_lag_pf(ldev, i); > + if (pf->dev == dev && pf->sd_fdb_active) { > + mlx5_lag_shared_fdb_destroy(ldev, pf->group_id); > + break; > + } > + } > + mutex_unlock(&ldev->lock); > + mlx5_devcom_comp_unlock(sd_devcom); > } > > void mlx5_lag_enable_change(struct mlx5_core_dev *dev)