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Thu, 31 Jul 2025 21:32:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEyRx/Pl7BjdxFzVTQWc6hVw7LnXbmjumZvBjBAl4aA+8La5UD8cNfMne03gb7c1tgo+RC+vA== X-Received: by 2002:a05:6a21:998b:b0:21a:da01:e0cf with SMTP id adf61e73a8af0-23dc0e32c0dmr19142810637.22.1754022739991; Thu, 31 Jul 2025 21:32:19 -0700 (PDT) Received: from [10.217.216.26] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-76bccfbcd00sm2994293b3a.60.2025.07.31.21.32.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 31 Jul 2025 21:32:19 -0700 (PDT) Message-ID: <784545d0-2173-4a8b-9d5d-bee11226351e@oss.qualcomm.com> Date: Fri, 1 Aug 2025 10:02:15 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/7] clk: qcom: Add TCSR clock driver for Glymur To: Abel Vesa Cc: kernel@oss.qualcomm.com, Pankaj Patil , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-0-227cfe5c8ef4@oss.qualcomm.com> <20250729-glymur-gcc-tcsrcc-rpmhcc-v3-3-227cfe5c8ef4@oss.qualcomm.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=Vdn3PEp9 c=1 sm=1 tr=0 ts=688c4355 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=ai6KDVl1yJewkkMvyeoA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: _5KjaQ3oKGjcC4B9ldbIUN92xQQm8fG6 X-Proofpoint-GUID: _5KjaQ3oKGjcC4B9ldbIUN92xQQm8fG6 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODAxMDAyOCBTYWx0ZWRfX0J52P4as1yyy wIHUSfAxr7ccZAr4FRLH7UcIKhUgfnoWJHkkGMPxcykYATpuH0S7XtT5OhXdYhJ0Y8KqbbKaBMe ZDRrTQfrDVibIyYBmN78MkKZtLCMNs6EaCkRsVyORmPaN/URDcdPbLKK7BJQNRrp7XUuak7eVlH 2AxwukHPwSPLJmsjU7JHMDqL2wkjEe8n3nKJOx/45C+nE7ngDxbxFoAlwclmM8b3i8DXvdj7sKE Ix5unuDR8lV3zc5dueSKsgblcnJrllfFlago4WSmmBQ7S9pNoD+Int4fiDhLgoGBuhnoQNdGk/C YCElxF2bYx//mk/zkWZsAm25C3KIjGrAKFotm+icrRIAjtcL0yn8eQmz/IIxrx8DltcoFi3nCtZ sW8gjFcJeyA7BIoxT4J440p64LqbP4o6O/xj9Mt4t38q5U7oN3IC35k99wgEUTTCmnj4g4wL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-31_04,2025-07-31_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxscore=0 lowpriorityscore=0 impostorscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 mlxlogscore=999 spamscore=0 phishscore=0 bulkscore=0 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2508010028 On 7/30/2025 4:55 PM, Abel Vesa wrote: > On 25-07-29 11:12:37, Taniya Das wrote: >> Add a clock driver for the TCSR clock controller found on Glymur, which >> provides refclks for PCIE, USB, and UFS. >> >> Signed-off-by: Taniya Das >> --- >> drivers/clk/qcom/Kconfig | 8 ++ >> drivers/clk/qcom/Makefile | 1 + >> drivers/clk/qcom/tcsrcc-glymur.c | 257 +++++++++++++++++++++++++++++++++++++++ >> 3 files changed, 266 insertions(+) >> > > [...] > >> + >> +static struct clk_branch tcsr_edp_clkref_en = { >> + .halt_reg = 0x1c, >> + .halt_check = BRANCH_HALT_DELAY, >> + .clkr = { >> + .enable_reg = 0x1c, >> + .enable_mask = BIT(0), >> + .hw.init = &(const struct clk_init_data) { >> + .name = "tcsr_edp_clkref_en", >> + .ops = &clk_branch2_ops, > > As discussed off-list, these clocks need to have the bi_tcxo as parent. > > Otherwise, as far as the CCF is concerned these clocks will have rate 0, > which is obviously not the case. > > Bringing this here since there is a disconnect between X Elite and > Glymur w.r.t this now. The ref clocks are not required to be have a parent of bi_tcxo as these ideally can be left enabled(as a subsystem requirement) even if HLOS (APSS) goes to suspend. With the bi_tcxo parent the ARC vote from HLOS/APSS will not allow APSS to collapse. If any consumers needs the clock rate, the driver should take the BI_TCXO handle. -- Thanks, Taniya Das