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Fri, 10 Oct 2025 04:17:43 -0700 (PDT) Message-ID: <7848e331-3d32-42ee-a05f-66ab40ef00be@tuxon.dev> Date: Fri, 10 Oct 2025 14:17:41 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/6] arm64: dts: renesas: r9a08g045: Add PCIe node To: Biju Das , "lpieralisi@kernel.org" , "kwilczynski@kernel.org" , "mani@kernel.org" , "robh@kernel.org" , "bhelgaas@google.com" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "geert+renesas@glider.be" , "magnus.damm" , "p.zabel@pengutronix.de" Cc: "linux-pci@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Claudiu Beznea , wsa+renesas References: <20251007133657.390523-1-claudiu.beznea.uj@bp.renesas.com> <20251007133657.390523-4-claudiu.beznea.uj@bp.renesas.com> From: Claudiu Beznea Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, Biju, On 10/7/25 16:44, Biju Das wrote: > Hi Claudiu, > >> -----Original Message----- >> From: Claudiu >> Sent: 07 October 2025 14:37 >> Subject: [PATCH v5 3/6] arm64: dts: renesas: r9a08g045: Add PCIe node >> >> From: Claudiu Beznea >> >> The RZ/G3S SoC has a variant (R9A08G045S33) which supports PCIe. Add the PCIe node. >> >> Tested-by: Wolfram Sang >> Reviewed-by: Geert Uytterhoeven >> Signed-off-by: Claudiu Beznea >> --- >> >> Changes in v5: >> - updated the last part of ranges and dma-ranges >> - collected tags >> >> Changes in v4: >> - moved the node to r9a08g045.dtsi >> - dropped the "s33" from the compatible string >> - added port node >> - re-ordered properties to have them grouped together >> >> Changes in v3: >> - collected tags >> - changed the ranges flags >> >> Changes in v2: >> - updated the dma-ranges to reflect the SoC capability; added a >> comment about it. >> - updated clock-names, interrupt names >> - dropped legacy-interrupt-controller node >> - added interrupt-controller property >> - moved renesas,sysc at the end of the node to comply with >> DT coding style >> >> arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 66 ++++++++++++++++++++++ >> 1 file changed, 66 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi >> index 16e6ac614417..00b43377877e 100644 >> --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi >> +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi >> @@ -717,6 +717,72 @@ eth1: ethernet@11c40000 { >> status = "disabled"; >> }; >> >> + pcie: pcie@11e40000 { >> + compatible = "renesas,r9a08g045-pcie"; >> + reg = <0 0x11e40000 0 0x10000>; >> + ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>; >> + /* Map all possible DRAM ranges (4 GB). */ >> + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 1 0x00000000>; > > On RZ/G3E, HW manual mentions PCIe can access up to a 36-bit address space (access to DDR and PCIE0). > > Not sure about RZ/G3S? As of my knowledge/investigation, according to chapter 5.4.2.1 34-Bit Address Space Access of HW manual, revision 1.10, on RZ/G3S there are some bus masters that can access up to 34-bit address space, these being SDHI/eMMC, GEthernet, USB2.0, DMAC. The rest can access up to 32-bit address space. Thank you, Claudiu