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[24.4.73.83]) by smtp.gmail.com with ESMTPSA id h15-20020a170902680f00b00186cf82717fsm1578086plk.165.2022.11.03.22.13.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 03 Nov 2022 22:13:06 -0700 (PDT) Message-ID: <784babf1-ca2b-0a7e-7bdb-c767304c3dd5@rivosinc.com> Date: Thu, 3 Nov 2022 22:13:04 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.2.2 Subject: Re: [PATCH v12 07/17] riscv: Add vector struct and assembler definitions Content-Language: en-US To: Chris Stillson Cc: Greentime Hu , Vincent Chen , Paul Walmsley , Palmer Dabbelt , Albert Ou , Eric Biederman , Kees Cook , Anup Patel , Atish Patra , Oleg Nesterov , Guo Ren , Heinrich Schuchardt , Mayuresh Chitale , Conor Dooley , Paolo Bonzini , Qinglin Pan , Alexandre Ghiti , Arnd Bergmann , Andy Chiu , linux-riscv , lkml References: <20220921214439.1491510-1-stillson@rivosinc.com> <20220921214439.1491510-7-stillson@rivosinc.com> From: Vineet Gupta In-Reply-To: <20220921214439.1491510-7-stillson@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/21/22 14:43, Chris Stillson wrote: > From: Greentime Hu > > Add vector state context struct in struct thread and asm-offsets.c > definitions. > > The vector registers will be saved in datap pointer of __riscv_v_state. It > will be dynamically allocated in kernel space. It will be put right after > the __riscv_v_state data structure in user space. "Vector state includes vector reg file and additional dynamic configuration CSRs. To handle variable sized reg file context (due to implementation defined ref size) and to enable lazy-allocation of this, there's datap which points to appropriate location on user/kernel mode stack as relevant..." Something like above. > diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h > index 19eedd4af4cd..95917a2b24f9 100644 > --- a/arch/riscv/include/asm/processor.h > +++ b/arch/riscv/include/asm/processor.h > @@ -39,6 +39,7 @@ struct thread_struct { > unsigned long s[12]; /* s[0]: frame pointer */ > struct __riscv_d_ext_state fstate; > unsigned long bad_cause; > + struct __riscv_v_state vstate; I think this patch should be preparatory, don't wire up the vstate in thread_struct now. Only do it when the save/restore calls are wired up in low level code. > +struct __riscv_v_state { > + unsigned long vstart; > + unsigned long vl; > + unsigned long vtype; > + unsigned long vcsr; > + void *datap; > + /* > + * In signal handler, datap will be set a correct user stack offset > + * and vector registers will be copied to the address of datap > + * pointer. > + * > + * In ptrace syscall, datap will be set to zero and the vector > + * registers will be copied to the address right after this > + * structure. > + */ Nice. > > + OFFSET(RISCV_V_STATE_VSTART, __riscv_v_state, vstart); > + OFFSET(RISCV_V_STATE_VL, __riscv_v_state, vl); > + OFFSET(RISCV_V_STATE_VTYPE, __riscv_v_state, vtype); > + OFFSET(RISCV_V_STATE_VCSR, __riscv_v_state, vcsr); > + OFFSET(RISCV_V_STATE_DATAP, __riscv_v_state, datap); > + Ok. Also move the __vstate_{save,restore} functions from patch 5/17 here.