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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Spam-Flag: NO X-Spam-Score: -4.51 X-Rspamd-Action: no action X-Spamd-Result: default: False [-4.51 / 50.00]; BAYES_HAM(-3.00)[100.00%]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_DKIM_ALLOW(-0.20)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; FREEMAIL_TO(0.00)[huawei.com,oss.qualcomm.com,hisilicon.com,linaro.org,linux.intel.com,kernel.org,gmail.com,ffwll.ch]; FUZZY_RATELIMITED(0.00)[rspamd.com]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCPT_COUNT_TWELVE(0.00)[17]; MIME_TRACE(0.00)[0:+]; MID_RHS_MATCH_FROM(0.00)[]; FREEMAIL_ENVRCPT(0.00)[gmail.com]; DKIM_SIGNED(0.00)[suse.de:s=susede2_rsa,suse.de:s=susede2_ed25519]; RCVD_TLS_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:rdns,imap1.dmz-prg2.suse.org:helo,suse.de:email,suse.de:dkim,suse.de:mid,hisilicon.com:email,suse.com:url,huawei.com:email]; SPAMHAUS_XBL(0.00)[2a07:de40:b281:104:10:150:64:97:from]; DKIM_TRACE(0.00)[suse.de:+] X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Queue-Id: F02D0759FA X-Spam-Level: Am 09.05.26 um 05:23 schrieb Yongbang Shi: > From: Lin He > > In the past, we use width and height to look up our PLL value. > But actually the actual clock check is also necessnary. There are > some resolutions that width and height same, but its clock different. > Add the clock check when using pll_table to determine the PLL value. > > Fixes: da52605eea8f ("drm/hisilicon/hibmc: Add support for display engine") > Signed-off-by: Lin He > Signed-off-by: Yongbang Shi Reviewed-by: Thomas Zimmermann > --- > ChangeLog: > v5 -> v6: > - Modify the return values of `hibmc_get_best_clock_idx` and > `hibmc_crtc_mode_valid` > v2 -> v3: > - remove unused macro CLOCK_TOLERANCE. > v1 -> v2: > - remove tag "Reviewed-by: Tao Tian ", witch will > be given in public. > - add 'drm-misc-fixes' in subject prefix. > --- > .../gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 80 +++++++++++-------- > 1 file changed, 45 insertions(+), 35 deletions(-) > > diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c > index fd3f05ba62df..583670c7b60e 100644 > --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c > +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c > @@ -34,26 +34,43 @@ struct hibmc_display_panel_pll { > struct hibmc_dislay_pll_config { > u64 hdisplay; > u64 vdisplay; > + int clock; > u32 pll1_config_value; > u32 pll2_config_value; > }; > > static const struct hibmc_dislay_pll_config hibmc_pll_table[] = { > - {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ}, > - {800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, > - {1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, > - {1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, > - {1280, 768, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, > - {1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, > - {1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, > - {1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, > - {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ}, > - {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, > - {1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, > - {1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, > - {1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, > + {640, 480, 25000, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ}, > + {800, 600, 40000, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ}, > + {1024, 768, 65000, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ}, > + {1152, 864, 78750, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ}, > + {1280, 768, 80000, CRT_PLL1_HS_80MHZ, CRT_PLL2_HS_80MHZ}, > + {1280, 720, 74375, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ}, > + {1280, 960, 108000, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, > + {1280, 1024, 108000, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, > + {1440, 900, 105952, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ}, > + {1600, 900, 108000, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ}, > + {1600, 1200, 162500, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ}, > + {1920, 1080, 148750, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ}, > + {1920, 1200, 193750, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ}, > }; > > +static int hibmc_get_best_clock_idx(const struct drm_display_mode *mode) > +{ > + int i, diff; > + > + for (i = 0; i < ARRAY_SIZE(hibmc_pll_table); i++) { > + if (hibmc_pll_table[i].hdisplay == mode->hdisplay && > + hibmc_pll_table[i].vdisplay == mode->vdisplay) { > + diff = abs(mode->clock - hibmc_pll_table[i].clock); > + if (diff < mode->clock / 100) /* tolerance 1/100 */ > + return i; > + } > + } > + > + return -MODE_CLOCK_RANGE; > +} > + > static int hibmc_plane_atomic_check(struct drm_plane *plane, > struct drm_atomic_state *state) > { > @@ -213,19 +230,15 @@ static enum drm_mode_status > hibmc_crtc_mode_valid(struct drm_crtc *crtc, > const struct drm_display_mode *mode) > { > - size_t i = 0; > int vrefresh = drm_mode_vrefresh(mode); > > if (vrefresh < 59 || vrefresh > 61) > return MODE_NOCLOCK; > > - for (i = 0; i < ARRAY_SIZE(hibmc_pll_table); i++) { > - if (hibmc_pll_table[i].hdisplay == mode->hdisplay && > - hibmc_pll_table[i].vdisplay == mode->vdisplay) > - return MODE_OK; > - } > + if (hibmc_get_best_clock_idx(mode) >= 0) > + return MODE_OK; > > - return MODE_BAD; > + return MODE_CLOCK_RANGE; > } > > static u32 format_pll_reg(void) > @@ -280,23 +293,20 @@ static void set_vclock_hisilicon(struct drm_device *dev, u64 pll) > writel(val, priv->mmio + CRT_PLL1_HS); > } > > -static void get_pll_config(u64 x, u64 y, u32 *pll1, u32 *pll2) > +static void get_pll_config(struct drm_display_mode *mode, u32 *pll1, u32 *pll2) > { > - size_t i; > - size_t count = ARRAY_SIZE(hibmc_pll_table); > - > - for (i = 0; i < count; i++) { > - if (hibmc_pll_table[i].hdisplay == x && > - hibmc_pll_table[i].vdisplay == y) { > - *pll1 = hibmc_pll_table[i].pll1_config_value; > - *pll2 = hibmc_pll_table[i].pll2_config_value; > - return; > - } > + int idx; > + > + idx = hibmc_get_best_clock_idx(mode); > + if (idx < 0) { > + /* if found none, we use default value */ > + *pll1 = CRT_PLL1_HS_25MHZ; > + *pll2 = CRT_PLL2_HS_25MHZ; > + return; > } > > - /* if found none, we use default value */ > - *pll1 = CRT_PLL1_HS_25MHZ; > - *pll2 = CRT_PLL2_HS_25MHZ; > + *pll1 = hibmc_pll_table[idx].pll1_config_value; > + *pll2 = hibmc_pll_table[idx].pll2_config_value; > } > > /* > @@ -318,7 +328,7 @@ static u32 display_ctrl_adjust(struct drm_device *dev, > x = mode->hdisplay; > y = mode->vdisplay; > > - get_pll_config(x, y, &pll1, &pll2); > + get_pll_config(mode, &pll1, &pll2); > writel(pll2, priv->mmio + CRT_PLL2_HS); > set_vclock_hisilicon(dev, pll1); > -- -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Frankenstr. 146, 90461 Nürnberg, Germany, www.suse.com GF: Jochen Jaser, Andrew McDonald, Werner Knoblich, (HRB 36809, AG Nürnberg)