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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-be5095a1d85sm160891a12.26.2025.11.26.18.27.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 26 Nov 2025 18:27:59 -0800 (PST) Message-ID: <78956452-7c22-4338-823d-bc3d619cef7d@oss.qualcomm.com> Date: Thu, 27 Nov 2025 10:27:52 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 12/13] coresight: Allow setting the timestamp interval To: James Clark , Suzuki K Poulose , Mike Leach , Alexander Shishkin , Jonathan Corbet , Leo Yan , Randy Dunlap Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org References: <20251126-james-cs-syncfreq-v7-0-7fae5e0e5e16@linaro.org> <20251126-james-cs-syncfreq-v7-12-7fae5e0e5e16@linaro.org> Content-Language: en-US From: Jie Gan In-Reply-To: <20251126-james-cs-syncfreq-v7-12-7fae5e0e5e16@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: X-2lxW7zQsuNUJ0XfiPesbrG6IO5fxWY X-Authority-Analysis: v=2.4 cv=MIVtWcZl c=1 sm=1 tr=0 ts=6927b731 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=7CQSdrXTAAAA:8 a=KKAkSRfTAAAA:8 a=ANtGpvVd1iEdTLDb4B8A:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 a=a-qgeE7W1pNrGK8U0ZQC:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: X-2lxW7zQsuNUJ0XfiPesbrG6IO5fxWY X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTI3MDAxOCBTYWx0ZWRfX4qKgGsSJzw8C 509tk33J673RiDiflTBfnJIixuSq06MWK41jJwjbSZaF1mGGBTjNmsGv5iN8pkEtzRPby4J9+tx rPhAUytuh9FazWKobPRcSsYqO2pzMvomRYZ6qpOvJax4r8wuUBUtz+HOVt7zfuLvW+KpuXKlk54 zRZfMungjmmXKXjI5JZiJvtsP1fp02KxL3UysNgInc0puxfU8NdWxNHWPl6Swrc48aySEbMyCfj YHF64YQbekCcvRCPXpFLrjSMemm7ltmebWIECLY4PoyUZ5XqP+J8h7gZjbGlotbAn53voGIV0Tl BdVi7Fq8PW+8GeAM4HupbPQrHWtZc2WVtNC+hqtH4osKa2+5IoTV0LSMlDJxMWeNDir97j1PmS1 PnUgfd2Xv2Jila502zRapQ5Ia3v7wQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-25_02,2025-11-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 spamscore=0 bulkscore=0 impostorscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511270018 On 11/26/2025 6:54 PM, James Clark wrote: > Timestamps are currently emitted at the maximum rate possible, which is > much too frequent for most use cases. Set the interval using the value > from the timestamp field. Granular control is not required, so save > space in the config by interpreting it as 2 ^ timestamp. And then 4 > bits (0 - 15) is enough to set the interval to be larger than the > existing SYNC timestamp interval. > > No sysfs mode support is needed for this attribute because counter > generated timestamps are only configured for Perf mode. > Tested on Qcom Sa8775p-ride with perf session. Tested-by: Jie Gan Thanks, Jie > Reviewed-by: Leo Yan > Tested-by: Leo Yan > Signed-off-by: James Clark > --- > drivers/hwtracing/coresight/coresight-etm-perf.h | 1 + > drivers/hwtracing/coresight/coresight-etm4x-core.c | 28 +++++++++++++++------- > 2 files changed, 20 insertions(+), 9 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h > index 24d929428633..128f80bb1443 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.h > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h > @@ -7,6 +7,7 @@ > #ifndef _CORESIGHT_ETM_PERF_H > #define _CORESIGHT_ETM_PERF_H > > +#include > #include > #include "coresight-priv.h" > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index c7bf73c8f2d7..0129b0502726 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -651,7 +651,7 @@ static void etm4_enable_sysfs_smp_call(void *info) > * +--------------+ > * | > * +------v-------+ > - * | Counter x | (reload to 1 on underflow) > + * | Counter x | (reload to 2 ^ timestamp on underflow) > * +--------------+ > * | > * +------v--------------+ > @@ -662,11 +662,25 @@ static void etm4_enable_sysfs_smp_call(void *info) > * | Timestamp Generator | (timestamp on resource y) > * +----------------------+ > */ > -static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) > +static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata, > + struct perf_event_attr *attr) > { > int ctridx; > int rselector; > struct etmv4_config *config = &drvdata->config; > + struct perf_event_attr max_timestamp = { > + .ATTR_CFG_FLD_timestamp_CFG = U64_MAX, > + }; > + > + /* timestamp may be 0 if deprecated_timestamp is used, so make min 1 */ > + u8 ts_level = max(1, ATTR_CFG_GET_FLD(attr, timestamp)); > + > + /* > + * Disable counter generated timestamps when timestamp == MAX. Leave > + * only SYNC timestamps. > + */ > + if (ts_level == ATTR_CFG_GET_FLD(&max_timestamp, timestamp)) > + return 0; > > /* No point in trying if we don't have at least one counter */ > if (!drvdata->nr_cntr) > @@ -704,12 +718,8 @@ static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata) > return -ENOSPC; > } > > - /* > - * Initialise original and reload counter value to the smallest > - * possible value in order to get as much precision as we can. > - */ > - config->cntr_val[ctridx] = 1; > - config->cntrldvr[ctridx] = 1; > + /* Initialise original and reload counter value. */ > + config->cntr_val[ctridx] = config->cntrldvr[ctridx] = 1 << (ts_level - 1); > > /* > * Trace Counter Control Register TRCCNTCTLRn > @@ -799,7 +809,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, > * order to correlate instructions executed on different CPUs > * (CPU-wide trace scenarios). > */ > - ret = etm4_config_timestamp_event(drvdata); > + ret = etm4_config_timestamp_event(drvdata, attr); > > /* > * No need to go further if timestamp intervals can't >