From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E2BB3B1EC2 for ; Tue, 12 May 2026 14:26:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595983; cv=none; b=Hj+HsVDU+gHSIwev6SdsydpxbG8fpKugNco8hi5ruzTooRz+QwRuKpQ4RKPrS5rPdseVl0YRUkStMcJerLHmTZ2LWF+zMnf24imbtuCSCHqkQm2HWKFxyR6UGAgZDTSiHIvs9+yCECjSUGdTQvXdr9F5n8fHRFrTjCXdcbUvL48= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595983; c=relaxed/simple; bh=yQY/GsFxh7GejqJJ6NJ9j2O6/F0XXnw6R5O0ycuRTWA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GIq/bLRczv+GuWmDyd9NT12u7+m0O7/FPQBblZcljP4v4fdkxctFWkX6Cy0jNaVlsmkFcycMQfFvX4x7Cyc6q6ifjiDnuR82CjUDNNdoS6GQmYH8jpdANP+hYHWnoUa77dh2219Js3ZOn5hZd8K1Q8aECfTiN3YHsk+zUdPUXBw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eF5XxOhq; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eF5XxOhq" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 60977C2BCB0; Tue, 12 May 2026 14:26:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778595983; bh=yQY/GsFxh7GejqJJ6NJ9j2O6/F0XXnw6R5O0ycuRTWA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eF5XxOhqVWoXj2uC/f0Kd8qR1+PeWmomXTY2PT8C2mPTOrISy6vp+dMmJpATIR6sn RsXT6M0nYUo9/r3H0+Wek0fKDVDiArmDfbL1ThSJF6njobovZtXyUAu5jDADdXQtyx k5110yplwjJl+TfgZOTCfXGGz1E1RJSdY5aCemj7ZCKyTxAyte+K4evPlopxBKD5gR RwL/HRC2IdNV3TGD6IwhsK5FagzZF1syZAQnYpPB/1JWcUkLlu3IR764awUXUN+qbE AY2cwDYOVtBHrlBgXnAzXSvXBv5DSTuK2JYUD0P64Y8Sl7Tx0VAfCTSo3uuoiZT7Rx oB+GWUFyDGAlw== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , Subject: [PATCH v2 2/3] x86/apic: Introduce a variable to track the number of EILVT registers Date: Tue, 12 May 2026 19:49:16 +0530 Message-ID: <78a4c3ddce65e2a79f23aea6fdc05faf4346d290.1778594390.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Future AMD processors will be increasing the number of EILVT registers. Rather than hardcoding the maximum EILVT register count and using that everywhere, introduce a variable to track the EILVT register count. The number of EILVT registers is exposed through the extended APIC Feature Register (APIC_EFEAT) bits 23:16. Use this to initialize the count and fall back to the current default (APIC_EILVT_NR_AMD_10H) if the count is not available. Export the new variable for KVM since it needs this for supporting extended APIC register space on AMD. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- http://lore.kernel.org/r/20260204074452.55453-3-manali.shukla@amd.com as a related series adding support for KVM and needing access to the EILVT register count. - Naveen arch/x86/include/asm/apic.h | 2 ++ arch/x86/include/asm/apicdef.h | 1 + arch/x86/kernel/apic/apic.c | 12 ++++++++++++ 3 files changed, 15 insertions(+) diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h index 9cd493d467d4..8b03c7a14706 100644 --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -74,6 +74,8 @@ enum apic_intr_mode_id { APIC_SYMMETRIC_IO_NO_ROUTING }; +extern unsigned int apic_eilvt_count; + /* * With 82489DX we can't rely on apic feature bit * retrieved via cpuid but still have to deal with diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h index bc125c4429dc..ba7657e75ad1 100644 --- a/arch/x86/include/asm/apicdef.h +++ b/arch/x86/include/asm/apicdef.h @@ -134,6 +134,7 @@ #define APIC_TDR_DIV_64 0x9 #define APIC_TDR_DIV_128 0xA #define APIC_EFEAT 0x400 +#define APIC_EFEAT_XLC(x) (((x) >> 16) & 0xff) #define APIC_ECTRL 0x410 #define APIC_SEOI 0x420 #define APIC_IER 0x480 diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index 8c614750a19b..ecbf15399399 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c @@ -342,6 +342,8 @@ static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) */ static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; +unsigned int apic_eilvt_count __ro_after_init; +EXPORT_SYMBOL_FOR_KVM(apic_eilvt_count); static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) { @@ -410,6 +412,15 @@ int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) } EXPORT_SYMBOL_GPL(setup_APIC_eilvt); +static __init void init_eilvt(void) +{ + if (cpu_feature_enabled(X86_FEATURE_EXTAPIC)) + apic_eilvt_count = APIC_EFEAT_XLC(apic_read(APIC_EFEAT)); + + if (!apic_eilvt_count && boot_cpu_data.x86_vendor == X86_VENDOR_AMD) + apic_eilvt_count = APIC_EILVT_NR_AMD_10H; +} + /* * Program the next event, relative to now */ @@ -2344,6 +2355,7 @@ static void __init apic_bsp_setup(bool upmode) if (upmode) apic_bsp_up_setup(); setup_local_APIC(); + init_eilvt(); enable_IO_APIC(); end_local_APIC_setup(); -- 2.54.0