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Sun, 28 Jun 2026 22:20:20 -0700 (PDT) X-Received: by 2002:a17:902:f644:b0:2c8:e13a:f23a with SMTP id d9443c01a7336-2c8e13af2bdmr84668375ad.28.1782710420014; Sun, 28 Jun 2026 22:20:20 -0700 (PDT) Received: from [10.218.5.114] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c9b3ca81bcsm36277785ad.82.2026.06.28.22.20.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 28 Jun 2026 22:20:19 -0700 (PDT) Message-ID: <78abffc7-3b3b-4fed-9d9b-cfa9fa3778cc@oss.qualcomm.com> Date: Mon, 29 Jun 2026 10:49:41 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC To: Konrad Dybcio , Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio Cc: Ajit Pandey , Taniya Das , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20260605-shikra-audiocorecc-v1-0-7ee6b5f2d928@oss.qualcomm.com> <20260605-shikra-audiocorecc-v1-3-7ee6b5f2d928@oss.qualcomm.com> <191c4b05-7d66-4338-8321-ebc593379f73@oss.qualcomm.com> Content-Language: en-US From: Imran Shaik In-Reply-To: <191c4b05-7d66-4338-8321-ebc593379f73@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=ObKoyBTY c=1 sm=1 tr=0 ts=6a420095 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=Rk4DF2lalsHHy-5JHz8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjI5MDA0MyBTYWx0ZWRfX0IgDdxThXWvp dtsuhd0hQlbut2zRA/+hgq2rRu4lhCM/67+phGDObXmB/5IrHmRddDUAiMQCvvnePbuDMbx38ti myqTTBC4CMzTbWH4+t1iJSV8+G2EWVbUlmiGwjmE/AN5YMCYK04CMaa1RrsgrsOt7piRrLqIjVi OQ0XW4BE6uoNnc/tj15rnlW3piCz5F817+Mbh1ijLEwor5FK3TPKzL+o2diJHb5ViGLPS+RMjMs Qu9f2UeCR6vKz7t5OKxuCGnm5s4nOZIAG9p3sFJx4yA79Le48XyKvBSR59n8gXqfXhBKxWPzT8o 6f9nE588mUP1Ecjm602Q6opB8QRDEr5WteQPloL7J9ZMHhc2qCBjYX2GPPyXv7gJI6ryIbwFDO0 XazC1JgOS92BXG7HaOWT5QB3cu8zUsYTisV2JpKqUv7TGprk1kLowE87oBMz/ySZA9gYmUPox2v CaA00G7OrUvUxYHpe3Q== X-Proofpoint-ORIG-GUID: JCFKi-mh4bJIoiuGBavTIcWrtyupqLD0 X-Proofpoint-GUID: JCFKi-mh4bJIoiuGBavTIcWrtyupqLD0 X-Proofpoint-Spam-Info: AW1haW4tMjYwNjI5MDA0MyBTYWx0ZWRfX2nKFEzu8+Cah uPJOaeVE0p/0wqSXZQLGTfvHDCPhtXtXF509KGIGBbv0IZFIcXGlZczW7U+7HGB7DmOqb1RzEnC JT2ptDn/Qqq63UL1079bEI26l7hBiJM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-29_01,2026-06-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 suspectscore=0 impostorscore=0 clxscore=1015 bulkscore=0 malwarescore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606290043 On 11-06-2026 04:57 pm, Konrad Dybcio wrote: > On 6/5/26 1:26 PM, Imran Shaik wrote: >> Add support for Audio Core Clock Controller (AUDIOCORECC) on Qualcomm >> Shikra SoC. The AUDIOCORECC clocks and resets support differs based on >> Audio subsystem enablement. In the CQM variant, both clocks and resets >> are required as Audio is on APPS, while in the CQS variant only reset >> control is required since Audio is handled on Modem. Handle these >> requirements using variant specific compatibles. >> >> Signed-off-by: Imran Shaik >> --- > > [...] > >> +static const struct qcom_reset_map audio_core_cc_shikra_resets[] = { >> + [AUDIO_CORE_CSR_RX_SWR_CGCR] = { 0x1c }, >> + [AUDIO_CORE_CSR_TX_SWR_CGCR] = { 0x30 }, > My bad, this also should be controlling the BIT(1) only from SW side, similar to existing drivers. I will update in the next series. > So these are not "real resets", but for the sake of existing art, we > can keep pretending they are > > bit 1 is HW_CTL (1->hw controlled) and bit 0 is taken into account only > if 1 is cleared > > existing drivers toggle the HW_CTRL bit (meaning it's an > maybe-on/surely-on switch rather than off/on).. do we need to rectify > that somehow? > No changes are needed to the existing logic, as Audio SW only needs to control the HW_CTL bit. By default (PoR), HW_CTL is asserted, so the CGCRs are controlled by hardware. For the audio use case, where HW gating isn’t required, software de-asserts HW_CTL, after which control shifts to bit 0 (set to 1 by default). Thanks, Imran