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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ae053edc0e9sm341317366b.54.2025.06.21.03.09.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 21 Jun 2025 03:09:46 -0700 (PDT) Message-ID: <78f0e4b5-19f6-45a0-b4dc-a1b519645567@oss.qualcomm.com> Date: Sat, 21 Jun 2025 12:09:42 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/8] dt-bindings: clock: qcom: Add NSS clock controller for IPQ5424 SoC To: Luo Jie , Krzysztof Kozlowski , Georgi Djakov , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Michael Turquette , Stephen Boyd , Philipp Zabel , Anusha Rao , Richard Cochran , Konrad Dybcio , Catalin Marinas , Will Deacon Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, quic_kkumarcs@quicinc.com, quic_linchen@quicinc.com, quic_leiwei@quicinc.com, quic_suruchia@quicinc.com, quic_pavir@quicinc.com References: <20250617-qcom_ipq5424_nsscc-v1-0-4dc2d6b3cdfc@quicinc.com> <20250617-qcom_ipq5424_nsscc-v1-5-4dc2d6b3cdfc@quicinc.com> <512e3355-a110-4e7c-ab43-04f714950971@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <512e3355-a110-4e7c-ab43-04f714950971@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 23ZAtpEaXzXd9X75n4jWm7aPJLcFiR3A X-Proofpoint-ORIG-GUID: 23ZAtpEaXzXd9X75n4jWm7aPJLcFiR3A X-Authority-Analysis: v=2.4 cv=OZGYDgTY c=1 sm=1 tr=0 ts=685684ec cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=P-IC7800AAAA:8 a=gEfo2CItAAAA:8 a=COk6AnOGAAAA:8 a=VwQbUJbxAAAA:8 a=LVulUOl5olkk-nN9es8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 a=d3PnA9EDa4IxuAV0gXij:22 a=sptkURWiP4Gy88Gu7hUp:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjIxMDA1OSBTYWx0ZWRfXw55mKBSBxVvC WXfa4csJOEtc/a4HBhvThCsvMK8atXJgtZrWIh5yLsvDaxsj94r1StXPKfZaOCAXoISiRCsIMXn TmXktuXB1bHpYcW5WQj/lVy/TkY2Ebn9SFao5/h25+fyL3ZZnJy1K+CGSkbvUMeA+ZXmLKlX73y Hb2qbb2OLzm4CIWSDDY/TqAaVGiyOQOdkIoiKXeSNzk69GuaXX+d3JH8KDwPfNkonRtzSSXWmGg kxHFJAxyu96CppelQoc1/5LoEH0PUe4LY8Ie1OgkvhnOrUIVk8HEj5nh4YkHAx6TqPE1p714/C7 kSg07RMF9Rg3Ys6WexfzBqDB8mvp8mbkEh9xpOm/9LH0PrZDNhTes5Q80TnGTu9OYSZh+f3y5+f z6BLGRTMcHnuf/YOQS7UQhv8qXu2VWkaSzhe0Q+Jgir08I3VCux8s7vjRXp0br0068JCz2pm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-21_02,2025-06-20_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 impostorscore=0 mlxlogscore=999 bulkscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 spamscore=0 mlxscore=0 malwarescore=0 clxscore=1015 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506210059 On 6/18/25 5:58 PM, Luo Jie wrote: > > > On 6/17/2025 10:49 PM, Krzysztof Kozlowski wrote: >> On 17/06/2025 14:06, Luo Jie wrote: >>> NSS clock controller provides the clocks and resets to the >>> networking blocks such as PPE (Packet Process Engine) and >>> UNIPHY (PCS) on IPQ5424 devices. >> >> Please wrap commit message according to Linux coding style / submission >> process (neither too early nor over the limit): >> https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/submitting-patches.rst#L597 >> > > OK. > >>> >>> Add the compatible "qcom,ipq5424-nsscc" support based on the >>> current IPQ9574 NSS clock controller DT binding file. >>> ICC clocks are always provided by the NSS clock controller >>> of IPQ9574 and IPQ5424, so add interconnect-cells as required >>> DT property. >>> >>> Also add master/slave ids for IPQ5424 networking interfaces, >>> which is used by nss-ipq5424 driver for providing interconnect >>> services using icc-clk framework. >>> >>> Signed-off-by: Luo Jie >>> --- >>>   .../bindings/clock/qcom,ipq9574-nsscc.yaml         | 66 +++++++++++++++++++--- >>>   include/dt-bindings/clock/qcom,ipq5424-nsscc.h     | 65 +++++++++++++++++++++ >>>   include/dt-bindings/interconnect/qcom,ipq5424.h    | 13 +++++ >>>   include/dt-bindings/reset/qcom,ipq5424-nsscc.h     | 46 +++++++++++++++ >>>   4 files changed, 182 insertions(+), 8 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml >>> index 17252b6ea3be..5bc2fe049b26 100644 >>> --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml >>> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml >>> @@ -4,7 +4,7 @@ >>>   $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml# >>>   $schema: http://devicetree.org/meta-schemas/core.yaml# >>>   -title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 >>> +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424 >>>     maintainers: >>>     - Bjorn Andersson >>> @@ -12,21 +12,25 @@ maintainers: >>>     description: | >>>     Qualcomm networking sub system clock control module provides the clocks, >>> -  resets on IPQ9574 >>> +  resets on IPQ9574 and IPQ5424 >>>   -  See also:: >>> +  See also: >>> +    include/dt-bindings/clock/qcom,ipq5424-nsscc.h >>>       include/dt-bindings/clock/qcom,ipq9574-nsscc.h >>> +    include/dt-bindings/reset/qcom,ipq5424-nsscc.h >>>       include/dt-bindings/reset/qcom,ipq9574-nsscc.h >>>     properties: >>>     compatible: >>> -    const: qcom,ipq9574-nsscc >>> +    enum: >>> +      - qcom,ipq5424-nsscc >>> +      - qcom,ipq9574-nsscc >>>       clocks: >>>       items: >>>         - description: Board XO source >>> -      - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source >>> -      - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source >>> +      - description: CMN_PLL NSS 1200 MHz or 300 MHZ (Bias PLL cc) clock source >>> +      - description: CMN_PLL PPE 353 MHz  or 375 MHZ (Bias PLL ubi nc) clock source >> >> This change means devices are different. Just ocme with your own schema. > > The NSS clock controller hardware block on the IPQ5424 SoC is identical > in design to that of the IPQ9574 SoC. The main difference is in the > clock rates for its two parent clocks sourced from the CMN PLL block. > > Given this, would it be acceptable to update the clock name and its > description to use a more generic clock name, such as "nss" and "ppe" > instead of the current "nss_1200" and "ppe_353"? Because you used those clock_names in the existing ipq9574, you can't change them now. You could introduce a separate set of clock_names for the new ipq5424 though, but I think it could be useful to drop the rate suffix for new additions Konrad