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X-CSE-ConnectionGUID: esCiC9rSSlKyc/NBe+KcpQ== X-CSE-MsgGUID: L4yJZeiUT5+oudBJvnEOfQ== X-IronPort-AV: E=McAfee;i="6800,10657,11531"; a="63979543" X-IronPort-AV: E=Sophos;i="6.17,312,1747724400"; d="scan'208";a="63979543" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Sep 2025 23:30:42 -0700 X-CSE-ConnectionGUID: VckSAqD6Tum9vhBQoBS0qA== X-CSE-MsgGUID: 67lBLui+TgiBT8+6JfOIJQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,265,1751266800"; d="scan'208";a="174974878" Received: from junlongf-mobl.ccr.corp.intel.com (HELO [10.238.1.52]) ([10.238.1.52]) by fmviesa009-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Sep 2025 23:30:39 -0700 Message-ID: <793a01d8-c439-45ee-a509-606245f42f07@intel.com> Date: Mon, 15 Sep 2025 14:30:36 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v15 11/41] KVM: x86: Report KVM supported CET MSRs as to-be-saved To: Sean Christopherson , Paolo Bonzini Cc: kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Tom Lendacky , Mathias Krause , John Allen , Rick Edgecombe , Chao Gao , Maxim Levitsky , Zhang Yi Z References: <20250912232319.429659-1-seanjc@google.com> <20250912232319.429659-12-seanjc@google.com> Content-Language: en-US From: Xiaoyao Li In-Reply-To: <20250912232319.429659-12-seanjc@google.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 9/13/2025 7:22 AM, Sean Christopherson wrote: > From: Yang Weijiang > > Add CET MSRs to the list of MSRs reported to userspace if the feature, > i.e. IBT or SHSTK, associated with the MSRs is supported by KVM. > > Suggested-by: Chao Gao > Signed-off-by: Yang Weijiang > Tested-by: Mathias Krause > Tested-by: John Allen > Tested-by: Rick Edgecombe > Signed-off-by: Chao Gao > Signed-off-by: Sean Christopherson Reviewed-by: Xiaoyao Li > --- > arch/x86/kvm/x86.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > index 5653ddfe124e..2c9908bc8b32 100644 > --- a/arch/x86/kvm/x86.c > +++ b/arch/x86/kvm/x86.c > @@ -344,6 +344,10 @@ static const u32 msrs_to_save_base[] = { > MSR_IA32_UMWAIT_CONTROL, > > MSR_IA32_XFD, MSR_IA32_XFD_ERR, MSR_IA32_XSS, > + > + MSR_IA32_U_CET, MSR_IA32_S_CET, > + MSR_IA32_PL0_SSP, MSR_IA32_PL1_SSP, MSR_IA32_PL2_SSP, > + MSR_IA32_PL3_SSP, MSR_IA32_INT_SSP_TAB, > }; > > static const u32 msrs_to_save_pmu[] = { > @@ -7598,6 +7602,20 @@ static void kvm_probe_msr_to_save(u32 msr_index) > if (!kvm_caps.supported_xss) > return; > break; > + case MSR_IA32_U_CET: > + case MSR_IA32_S_CET: > + if (!kvm_cpu_cap_has(X86_FEATURE_SHSTK) && > + !kvm_cpu_cap_has(X86_FEATURE_IBT)) > + return; > + break; > + case MSR_IA32_INT_SSP_TAB: > + if (!kvm_cpu_cap_has(X86_FEATURE_LM)) > + return; > + fallthrough; > + case MSR_IA32_PL0_SSP ... MSR_IA32_PL3_SSP: > + if (!kvm_cpu_cap_has(X86_FEATURE_SHSTK)) > + return; > + break; > default: > break; > }