From: Krzysztof Kozlowski <krzk@kernel.org>
To: "William A. Kennington III" <william@wkennington.com>,
Avi Fishman <avifishman70@gmail.com>,
Tomer Maimon <tmaimon77@gmail.com>,
Tali Perry <tali.perry1@gmail.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: openbmc@lists.ozlabs.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: Fix nuvoton 8xx clock properties
Date: Wed, 16 Apr 2025 08:55:11 +0200 [thread overview]
Message-ID: <79400920-22b4-4bce-b204-c58087495c22@kernel.org> (raw)
In-Reply-To: <20250415232521.2049906-1-william@wkennington.com>
On 16/04/2025 01:25, William A. Kennington III wrote:
> The latest iteration of the clock driver got rid of the separate clock
I don't see the binding deprecated.
> compatible node, merging clock and reset devices.
>
> Signed-off-by: William A. Kennington III <william@wkennington.com>
> ---
> .../boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 16 ++++++----------
> .../boot/dts/nuvoton/nuvoton-npcm845-evb.dts | 8 ++++++++
> 2 files changed, 14 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> index ecd171b2feba..4da62308b274 100644
> --- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> +++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
> @@ -47,17 +47,13 @@ ahb {
> interrupt-parent = <&gic>;
> ranges;
>
> - rstc: reset-controller@f0801000 {
> + clk: rstc: reset-controller@f0801000 {
> compatible = "nuvoton,npcm845-reset";
> reg = <0x0 0xf0801000 0x0 0x78>;
So now it lacks quite a bit of address space. This must be explained in
commit msg.
> #reset-cells = <2>;
> nuvoton,sysgcr = <&gcr>;
> - };
> -
> - clk: clock-controller@f0801000 {
> - compatible = "nuvoton,npcm845-clk";
> + clocks = <&refclk>;
> #clock-cells = <1>;
> - reg = <0x0 0xf0801000 0x0 0x1000>;
> };
>
> apb {
> @@ -81,7 +77,7 @@ timer0: timer@8000 {
> compatible = "nuvoton,npcm845-timer";
> interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x8000 0x1C>;
> - clocks = <&clk NPCM8XX_CLK_REFCLK>;
> + clocks = <&refclk>;
Not explained in commit msg.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-04-16 6:55 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-15 23:25 William A. Kennington III
2025-04-16 6:55 ` Krzysztof Kozlowski [this message]
2025-04-16 18:43 ` Tomer Maimon
2025-04-25 22:14 ` William Kennington
2025-04-25 22:16 ` William Kennington
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