From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D471CC6FA82 for ; Sat, 10 Sep 2022 10:53:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229522AbiIJKxY (ORCPT ); Sat, 10 Sep 2022 06:53:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229456AbiIJKxV (ORCPT ); Sat, 10 Sep 2022 06:53:21 -0400 Received: from mx3.wp.pl (mx3.wp.pl [212.77.101.9]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 358317549B for ; Sat, 10 Sep 2022 03:53:18 -0700 (PDT) Received: (wp-smtpd smtp.wp.pl 1134 invoked from network); 10 Sep 2022 12:53:15 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=wp.pl; s=1024a; t=1662807195; bh=ySIT/E9Gt09cmxMpPlzE5Vy+axb5DVXkBXG6cqkUlbA=; h=Subject:To:Cc:From; b=pSjJ7yhl30zGLZHJaOwWzCg+aLFhNWRw7QMA74OmvSSmzKvUzNEmgRZa0vfLk8FuC NenomNaZwQstKZhrLYzHm9u8bQbd9y4ckNEeDJ4opuD6XJO4xnOIpnOueIT/XaLJ7M Ky4jgg/D88SkfoZHxycdGNSej9fezo46aBXd0ddE= Received: from ip-137-21.ds.pw.edu.pl (HELO [192.168.3.133]) (olek2@wp.pl@[194.29.137.21]) (envelope-sender ) by smtp.wp.pl (WP-SMTPD) with ECDHE-RSA-AES256-GCM-SHA384 encrypted SMTP for ; 10 Sep 2022 12:53:15 +0200 Message-ID: <794a2039-cdf7-2676-482f-9913a8949647@wp.pl> Date: Sat, 10 Sep 2022 12:53:40 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second VPE Content-Language: en-US To: Thomas Bogendoerfer , Martin Blumenstingl Cc: Marc Zyngier , Sander Vanheule , Hauke Mehrtens , git@birger-koblitz.de, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org References: <20220702190705.5319-1-olek2@wp.pl> <3c9a032edd0fb9b9608ad3ca08d6e3cc38f21464.camel@svanheule.net> <87fsjen2kl.wl-maz@kernel.org> <20220706081901.GA10797@alpha.franken.de> <20220707100630.GC9894@alpha.franken.de> <20220707143930.GA14693@alpha.franken.de> From: Aleksander Bajkowski In-Reply-To: <20220707143930.GA14693@alpha.franken.de> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-WP-MailID: d28ee153a6549419ec426d4a137f785b X-WP-AV: skaner antywirusowy Poczty Wirtualnej Polski X-WP-SPAM: NO 000000C [geMU] Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi THomas, On 7/7/22 16:39, Thomas Bogendoerfer wrote: [...] >> Or can you point me to the code in >> drivers/irqchip/irq-mips-cpu.c that's responsible for enabling the >> interrupts on VPE 1 (is it simply unmask_mips_irq)? > > IMHO there is the problem, irq-mips-cpu.c can only do CPU irq operations > on the same CPU. I've checked MIPS MT specs and it's possible do > modify CP0 registers between VPEs. Using that needs changes in > irq-mips-cpu.c. But mabye that's not woth the effort as probably > all SMP cabable platforms have some multi processort capable > interrupt controller implemented. > > I thought about another way solve the issue. By introducing a > new function in smp-mt.c which sets the value of the interrupt > mask for the secondary CPU, which is then used in vsmp_init_secondary(). > Not sure if this is worth the effort compared to a .boot_secondary > override. Enabling interrupts on the second VPE using hotplug will be accepted upstream? Below is a sample patch. Unfortunately, this is not a generic solution. If in the future there are more platforms that require a similar patch, this can be converted into some generic solution. --- a/arch/mips/lantiq/irq.c +++ b/arch/mips/lantiq/irq.c @@ -335,6 +336,18 @@ static const struct irq_domain_ops irq_domain_ops = { .map = icu_map, }; +static int lantiq_cpu_starting(unsigned int cpu) +{ + /* + * MIPS CPU startup function vsmp_init_secondary() will only enable some of + * the interrupts for the second CPU/VPE. Fix this during hotplug. + */ + if (cpu > 0) + set_c0_status(ST0_IM); + + return 0; +} + int __init icu_of_init(struct device_node *node, struct device_node *parent) { struct device_node *eiu_node; @@ -410,6 +423,10 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent) } of_node_put(eiu_node); + cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LANTIQ_STARTING, + "arch/mips/lantiq:starting", + lantiq_cpu_starting, NULL); + return 0; } --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -152,6 +152,7 @@ enum cpuhp_state { CPUHP_AP_IRQ_RISCV_STARTING, CPUHP_AP_IRQ_LOONGARCH_STARTING, CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, + CPUHP_AP_IRQ_LANTIQ_STARTING, CPUHP_AP_ARM_MVEBU_COHERENCY, CPUHP_AP_MICROCODE_LOADER, CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING, Best regards, Aleksander