Re: LPC Bus Driver

[John Garry <john.garry@huawei.com>]

+ add fpga list and Greg+Arnd for misc drivers

Hi Luis,

> 
> We have this board with our own SoC, which is connected to an external CPLD (FPGA) via LPC (low pin count) bus.
> I've been doing some research to see what the best way of designing the drivers for it would be, and came across the Hisilicon LPC driver stuff (which I believe you're the maintainer for).
> 
> Just a little background. Let's say our host (ARM) has a custom LPC controller. The LPC controller let's us perform reads/writes of CPLD registers via LPC bus. This CPLD is the only slave device attached to that bus and we only use it for reading/writing certain
>   registers (e.g., we use it to access some system information and for resetting the ARM during reboot).
> 
> I was looking at the regmap framework and that seemed a good way to go. 

I thought that regmap only allows mapping in MMIO regions for 
multiplexing access from multiple drivers or accessing registers outside 
the device HW registers, but you seem to need to manually generate the 
LPC bus accesses to access registers on the slave device.

If this FPGA is the only device which will ever be on this LPC bus, then 
could you encode the LPC accesses directly in the FPGA driver?

 > But then I saw the logic_pio stuff as well and now I'm not sure what 
the best approach would be anymore

Logic PIO is for IO Port accesses. It could serve your purpose, but you 
would need to use IO port accesses for your slave driver, like inb and outb.

As another alternative, it might be worth considering writing an I2C 
controller driver for your LPC host, i.e. model as an I2C bus, and have 
an I2C client driver for the LPC slave (FPGA). I think that there are 
examples of this in the kernel.

All the best,
john