Re: [PATCH v4 01/19] dt-bindings: ARM: MediaTek: Add new MT8188 clock

["Garmin Chang (張家銘)" <Garmin.Chang@mediatek.com>]

On Tue, 2023-01-17 at 12:39 +0100, Krzysztof Kozlowski wrote:
> On 09/01/2023 13:44, Garmin.Chang wrote:
> > Add the new binding documentation for system clock
> > and functional clock on MediaTek MT8188.
> 
> Use subject prefixes matching the subsystem (which you can get for
> example with `git log --oneline -- DIRECTORY_OR_FILE` on the
> directory
> your patch is touching).
> 
Thanks for your suggestions.
I will change the subject as "dt-bindings: clock: mediatek: Add new
MT8188 clock".

> > 
> > Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> > ---
> >  .../bindings/clock/mediatek,mt8188-clock.yaml |  71 ++
> >  .../clock/mediatek,mt8188-sys-clock.yaml      |  55 ++
> >  .../dt-bindings/clock/mediatek,mt8188-clk.h   | 733
> > ++++++++++++++++++
> >  3 files changed, 859 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
> >  create mode 100644
> > Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-
> > clock.yaml
> >  create mode 100644 include/dt-bindings/clock/mediatek,mt8188-clk.h
> > 
> > diff --git
> > a/Documentation/devicetree/bindings/clock/mediatek,mt8188-
> > clock.yaml
> > b/Documentation/devicetree/bindings/clock/mediatek,mt8188-
> > clock.yaml
> > new file mode 100644
> > index 000000000000..6654cead71f6
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-
> > clock.yaml
> > @@ -0,0 +1,71 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: 
> > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!gjq5d864kzewW48Dn7ze9jNV_MmGdrCJa8uDamXLOfnmQu0ht02CQMJxiH_q2Z_QZYLb5Wru5b0ylzq_DSsImlKkUSgRzko$ 
> >  
> > +$schema: 
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!gjq5d864kzewW48Dn7ze9jNV_MmGdrCJa8uDamXLOfnmQu0ht02CQMJxiH_q2Z_QZYLb5Wru5b0ylzq_DSsImlKkIcrakCc$ 
> >  
> > +
> > +title: MediaTek Functional Clock Controller for MT8188
> > +
> > +maintainers:
> > +  - Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +description: |
> > +  The clock architecture in MediaTek like below
> > +  PLLs -->
> > +          dividers -->
> > +                      muxes
> > +                           -->
> > +                              clock gate
> > +
> > +  The devices provide clock gate control in different IP blocks.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - mediatek,mt8188-adsp-audio26m
> > +      - mediatek,mt8188-imp-iic-wrap-c
> > +      - mediatek,mt8188-imp-iic-wrap-en
> > +      - mediatek,mt8188-imp-iic-wrap-w
> > +      - mediatek,mt8188-mfgcfg
> > +      - mediatek,mt8188-vppsys0
> > +      - mediatek,mt8188-wpesys
> > +      - mediatek,mt8188-wpesys-vpp0
> > +      - mediatek,mt8188-vppsys1
> > +      - mediatek,mt8188-imgsys
> > +      - mediatek,mt8188-imgsys-wpe1
> > +      - mediatek,mt8188-imgsys-wpe2
> > +      - mediatek,mt8188-imgsys-wpe3
> > +      - mediatek,mt8188-imgsys1-dip-top
> > +      - mediatek,mt8188-imgsys1-dip-nr
> > +      - mediatek,mt8188-ipesys
> > +      - mediatek,mt8188-camsys
> > +      - mediatek,mt8188-camsys-rawa
> > +      - mediatek,mt8188-camsys-yuva
> > +      - mediatek,mt8188-camsys-rawb
> > +      - mediatek,mt8188-camsys-yuvb
> > +      - mediatek,mt8188-ccusys
> > +      - mediatek,mt8188-vdecsys-soc
> > +      - mediatek,mt8188-vdecsys
> > +      - mediatek,mt8188-vencsys
> 
> The list should be ordered by name.
> 
Ok, I will modify in alphabetical order.

> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  '#clock-cells':
> > +    const: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - '#clock-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    clock-controller@11283000 {
> > +        compatible = "mediatek,mt8188-imp-iic-wrap-c";
> > +        reg = <0x11283000 0x1000>;
> > +        #clock-cells = <1>;
> > +    };
> > +
> > diff --git
> > a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-
> > clock.yaml
> > b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-
> > clock.yaml
> > new file mode 100644
> > index 000000000000..541e0f7df79f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-
> > clock.yaml
> > @@ -0,0 +1,55 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: 
> > https://urldefense.com/v3/__http://devicetree.org/schemas/arm/mediatek/mediatek,mt8188-sys-clock.yaml*__;Iw!!CTRNKA9wMg0ARbw!gjq5d864kzewW48Dn7ze9jNV_MmGdrCJa8uDamXLOfnmQu0ht02CQMJxiH_q2Z_QZYLb5Wru5b0ylzq_DSsImlKkT6xBhoI$ 
> >  
> > +$schema: 
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!gjq5d864kzewW48Dn7ze9jNV_MmGdrCJa8uDamXLOfnmQu0ht02CQMJxiH_q2Z_QZYLb5Wru5b0ylzq_DSsImlKkIcrakCc$ 
> >  
> > +
> > +title: MediaTek System Clock Controller for MT8188
> > +
> > +maintainers:
> > +  - Garmin Chang <garmin.chang@mediatek.com>
> > +
> > +description: |
> > +  The clock architecture in MediaTek like below
> > +  PLLs -->
> > +          dividers -->
> > +                      muxes
> > +                           -->
> > +                              clock gate
> > +
> > +  The apmixedsys provides most of PLLs which generated from SoC
> > 26m.
> > +  The topckgen provides dividers and muxes which provide the clock
> > source to other IP blocks.
> > +  The infracfg_ao provides clock gate in peripheral and
> > infrastructure IP blocks.
> > +  The mcusys provides mux control to select the clock source in AP
> > MCU.
> > +  The device nodes also provide the system control capacity for
> > configuration.
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - enum:
> > +          - mediatek,mt8188-topckgen
> > +          - mediatek,mt8188-infracfg-ao
> > +          - mediatek,mt8188-apmixedsys
> > +          - mediatek,mt8188-pericfg-ao
> 
> Ditto
> 
Ok, I will modify in alphabetical order.

> 
> Best regards,
> Krzysztof
>