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Wed, 24 Sep 2025 09:00:33 -0700 (PDT) Received: from [10.1.1.59] ([80.111.64.44]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46e32bf95f6sm549345e9.2.2025.09.24.09.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Sep 2025 09:00:33 -0700 (PDT) Message-ID: <798600a43825818bcf828da7060f38105f7f3225.camel@linaro.org> Subject: Re: [PATCH v5 4/5] clk: samsung: add Exynos ACPM clock driver From: =?ISO-8859-1?Q?Andr=E9?= Draszik To: Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , Michael Turquette , Stephen Boyd , Krzysztof Kozlowski , Alim Akhtar , Sylwester Nawrocki , Chanwoo Choi , Catalin Marinas , Will Deacon Cc: linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, willmcvicker@google.com, kernel-team@android.com Date: Wed, 24 Sep 2025 17:00:31 +0100 In-Reply-To: <20250924-acpm-clk-v5-4-4cca1fadd00d@linaro.org> References: <20250924-acpm-clk-v5-0-4cca1fadd00d@linaro.org> <20250924-acpm-clk-v5-4-4cca1fadd00d@linaro.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Tudor, On Wed, 2025-09-24 at 15:11 +0000, Tudor Ambarus wrote: > Add the Exynos ACPM clock driver. It provides support for clocks that > are controlled by firmware that implements the ACPM interface. [...] > diff --git a/drivers/clk/samsung/clk-acpm.c b/drivers/clk/samsung/clk-acp= m.c > new file mode 100644 > index 0000000000000000000000000000000000000000..9e8354168a63b1427c2f3faf1= 5e4e7955e924dc8 > --- /dev/null > +++ b/drivers/clk/samsung/clk-acpm.c > @@ -0,0 +1,185 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Samsung Exynos ACPM protocol based clock driver. > + * > + * Copyright 2025 Linaro Ltd. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +struct acpm_clk { > + u32 id; > + struct clk_hw hw; > + unsigned int mbox_chan_id; > + const struct acpm_handle *handle; > +}; > + > +struct acpm_clk_variant { > + const char *name; > +}; > + > +struct acpm_clk_driver_data { > + const struct acpm_clk_variant *clks; > + unsigned int nr_clks; > + unsigned int mbox_chan_id; > +}; > + > +#define to_acpm_clk(clk) container_of(clk, struct acpm_clk, hw) > + > +#define ACPM_CLK(cname) \ > + { \ > + .name =3D cname, \ > + } > + > +static const struct acpm_clk_variant gs101_acpm_clks[] =3D { > + ACPM_CLK("mif"), > + ACPM_CLK("int"), > + ACPM_CLK("cpucl0"), > + ACPM_CLK("cpucl1"), > + ACPM_CLK("cpucl2"), > + ACPM_CLK("g3d"), > + ACPM_CLK("g3dl2"), > + ACPM_CLK("tpu"), > + ACPM_CLK("intcam"), > + ACPM_CLK("tnr"), > + ACPM_CLK("cam"), > + ACPM_CLK("mfc"), > + ACPM_CLK("disp"), > + ACPM_CLK("b0"), The last one should be 'bo' (bigocean), not b0. Cheers, Andre'