From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF446192589; Mon, 25 Nov 2024 11:08:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732532891; cv=none; b=nvvOugNzEnC0MT5MdBimCCN1b0y5LIUgiEZIlXemhkIgSHi+T6lUZuqtAbX//TBfh/gUSXGKBck+dUex1VBtMSya73LxENhO6YnxHzz2UphpG6guHic6Ta0g57TVxbc+IUrBR4K5c7QKtU6rCma/FKAmK/9yg45p/auCdhb+9Ps= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1732532891; c=relaxed/simple; bh=eKZ3NTtyLru4te3bIet0CwHqjzzmKZtcG0wMs7PZ2w4=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=G45I7TSrdC92BdOM4ZLIC5XE7sbRc2JNdv3WpjfNQfFQJcPW4TgLpg8451/mpKpZiyikve9bipnSF5e0pJ+9kf+nHUUhdyULPORkI47RHBSxbiyaqpf2dX1JCFHUi8T936j3ugWfyWee/S9cL0S2xE+DLda4JSW38lY/KLAleHE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=mZRHJVA8; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="mZRHJVA8" Received: from [192.168.88.20] (91-157-155-49.elisa-laajakaista.fi [91.157.155.49]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 354996B5; Mon, 25 Nov 2024 12:07:44 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1732532864; bh=eKZ3NTtyLru4te3bIet0CwHqjzzmKZtcG0wMs7PZ2w4=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=mZRHJVA8sseG1Gmr8AcwOpOyshbXvvaqxf0Yh506PLb3LA18dn1vl5Y8eceumjrGo ItYh9QbNdeMUqkJqaEPgnJI+MGOR9lTz2hfP8O2vqyoOZ5njFbSFdpcdFWzjMeMgt5 +pcBTndCDtjCIrzid62CfAwnB6yCoNNfF9rdpMhg= Message-ID: <798adbca-7384-4c94-915d-f2cf0710b4e7@ideasonboard.com> Date: Mon, 25 Nov 2024 13:08:02 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/7] drm/tidss: Fix issue in irq handling causing irq-flood issue To: Aradhya Bhatia , Devarsh Thakkar , Jyri Sarha Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jonathan Cormier , Bin Liu , stable@vger.kernel.org References: <20241021-tidss-irq-fix-v1-0-82ddaec94e4a@ideasonboard.com> <20241021-tidss-irq-fix-v1-1-82ddaec94e4a@ideasonboard.com> Content-Language: en-US From: Tomi Valkeinen Autocrypt: addr=tomi.valkeinen@ideasonboard.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, On 24/11/2024 19:18, Aradhya Bhatia wrote: > Hi Tomi, Devarsh, > > On 10/21/24 19:37, Tomi Valkeinen wrote: >> It has been observed that sometimes DSS will trigger an interrupt and >> the top level interrupt (DISPC_IRQSTATUS) is not zero, but the VP and >> VID level interrupt-statuses are zero. > > Does this mean that there was a legitimate interrupt that potentially > went unrecognized? Or that there was a, for the lack of a better word, > fake interrupt trigger that doesn't need handling but just clearing? I don't have an answer to that. I haven't been able to trigger this issue, and I guess it's difficult to say for certain in any case. My guess is that it's some kind of race issue either in the HW or the combination of HW+SW. >> As the top level irqstatus is supposed to tell whether we have VP/VID >> interrupts, the thinking of the driver authors was that this particular >> case could never happen. Thus the driver only clears the DISPC_IRQSTATUS >> bits which has corresponding interrupts in VP/VID status. So when this >> issue happens, the driver will not clear DISPC_IRQSTATUS, and we get an >> interrupt flood. >> >> It is unclear why the issue happens. It could be a race issue in the >> driver, but no such race has been found. It could also be an issue with >> the HW. However a similar case can be easily triggered by manually >> writing to DISPC_IRQSTATUS_RAW. This will forcibly set a bit in the >> DISPC_IRQSTATUS and trigger an interrupt, and as the driver never clears >> the bit, we get an interrupt flood. >> >> To fix the issue, always clear DISPC_IRQSTATUS. The concern with this >> solution is that if the top level irqstatus is the one that triggers the >> interrupt, always clearing DISPC_IRQSTATUS might leave some interrupts >> unhandled if VP/VID interrupt statuses have bits set. However, testing >> shows that if any of the irqstatuses is set (i.e. even if >> DISPC_IRQSTATUS == 0, but a VID irqstatus has a bit set), we will get an >> interrupt. > > Does this mean if VID/VP irqstatus has been set right around the time > the equivalent DISPC_IRQSTATUS bit is being cleared, the equivalent > DISPC_IRQSTATUS bit is going to get set again, and make the driver > handle the event as we expect it to? (If I recall right) no, DISPC_IRQSTATUS won't be set. But it doesn't matter, the interrupt will be triggered anyway, and the driver will handle the interrupt. >> >> Signed-off-by: Tomi Valkeinen >> Co-developed-by: Bin Liu >> Signed-off-by: Bin Liu >> Co-developed-by: Devarsh Thakkar >> Signed-off-by: Devarsh Thakkar >> Co-developed-by: Jonathan Cormier >> Signed-off-by: Jonathan Cormier >> Fixes: 32a1795f57ee ("drm/tidss: New driver for TI Keystone platform Display SubSystem") >> Cc: stable@vger.kernel.org >> --- >> drivers/gpu/drm/tidss/tidss_dispc.c | 12 ++++-------- >> 1 file changed, 4 insertions(+), 8 deletions(-) >> >> diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/tidss_dispc.c >> index 1ad711f8d2a8..f81111067578 100644 >> --- a/drivers/gpu/drm/tidss/tidss_dispc.c >> +++ b/drivers/gpu/drm/tidss/tidss_dispc.c >> @@ -780,24 +780,20 @@ static >> void dispc_k3_clear_irqstatus(struct dispc_device *dispc, dispc_irq_t clearmask) >> { >> unsigned int i; >> - u32 top_clear = 0; >> >> for (i = 0; i < dispc->feat->num_vps; ++i) { >> - if (clearmask & DSS_IRQ_VP_MASK(i)) { >> + if (clearmask & DSS_IRQ_VP_MASK(i)) >> dispc_k3_vp_write_irqstatus(dispc, i, clearmask); >> - top_clear |= BIT(i); >> - } >> } >> for (i = 0; i < dispc->feat->num_planes; ++i) { >> - if (clearmask & DSS_IRQ_PLANE_MASK(i)) { >> + if (clearmask & DSS_IRQ_PLANE_MASK(i)) >> dispc_k3_vid_write_irqstatus(dispc, i, clearmask); >> - top_clear |= BIT(4 + i); >> - } >> } > > nit: Maybe these for-loop braces could be dropped as well. I like to have braces if there are multiple lines under it. > Otherwise, LGTM, > > Reviewed-by: Aradhya Bhatia Thanks! Tomi